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Sven Meier

Founder / CEO / FPGA Designer at NetTimeLogic GmbH
Intro Book
Experienced FPGA designer and CEO with expertise in embedded systems and software development.
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Location
Zurich, Switzerland, CH
Languages
  • Englisch Full professional proficiency
  • Deutsch Native or bilingual proficiency
Skills
  • Field Programmable Gate Arrays
  • Eingebettete Systeme
  • C
  • Softwareentwicklung
  • Eingebettete Software
  • Show all
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Bio

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Sven Meier is a seasoned FPGA designer and CEO with 9+ years of experience in embedded systems, software development, and product management. He holds degrees in Information Technology and Business Information Technology from ZHAW School of Engineering and ZHAW School of Management and Law.

Credentials

  • MAS Business Information Technology
    ZHAW School of Management and Law
    Jun, 2009
    - Apr, 2026
  • Dipl. Ing. FH Information Technology
    ZHAW School of Engineering
    Oct, 2004
    - Apr, 2026

Experience

  • NetTimeLogic GmbH
    • Zürich
    • Founder / CEO / FPGA Designer
      • Mar 2015 - Present
      • Zürich

      Everything

  • Enclustra GmbH
    • Zürich
    • FPGA Development Engineer / Product Manager / Project Leader
      • Jan 2013 - Aug 2016
      • Zürich

  • Noser Engineering AG
    • Winterthur und Umgebung, Schweiz
    • Development Engineer / Project Leader
      • Jul 2009 - Dec 2012
      • Winterthur und Umgebung, Schweiz

  • ZHAW School of Engineering
    • Winterthur und Umgebung, Schweiz
    • Development Engineer / Wissenschaftlicher Mitarbeiter
      • Dec 2004 - Jun 2009
      • Winterthur und Umgebung, Schweiz

  • Teletronics Technology Corporation
    • Newton PA USA
    • Engineering Consultant
      • Jul 2005 - Dec 2005
      • Newton PA USA

Education

  • 2001 - 2004
    ZHAW School of Engineering
    Dipl. Ing. IT FH, Informationstechnologie
  • 2007 - 2009
    ZHAW School of Management and Law
    MAS WI FH, Wirtschaftsinformatik

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Industry Focus. “Software Development”

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