Bio
Generated by
Topline AI
Steven Taetzsch is a seasoned verification engineer with extensive experience in System Verilog, Functional Verification, and hardware design. He has worked with top companies like Extreme Networks and Enterasys Networks, and has a strong background in ASIC and FPGA verification.
With a Bachelor's degree in Electrical Engineering from the University of Massachusetts Lowell, Steven has developed a solid foundation in digital design and verification. His expertise in Python scripting and system-level verification tools makes him a valuable asset to any organization.
As a seasoned engineer, Steven has a proven track record of delivering high-quality verification environments and scripts, and has a strong understanding of the latest verification tools and technologies.
Experience
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Extreme Networks
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Salem, NH
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Verification Engineer
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Apr 2006 - May 2015
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Salem, NH
System Verilog VMM based verification environments.Python scripting.
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ASIC/FPGA Verification Engineer
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2006 - May 2015
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Zaiq Technologies
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Woburn, Massachusettes
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Verification Engineer
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1999 - 2006
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Woburn, Massachusettes
ASIC/FPGA Verification consultant.
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PictureTel
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Andover Massachusettes
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Principal Engineer
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1995 - 1999
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Andover Massachusettes
Image Processing.FPGA design.
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Memotec, formally Infinet
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North Andover, MA
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Engineer
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1989 - 1997
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North Andover, MA
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Education
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1982 - 1985University of Massachusetts Lowell
Suggested Services
This profile is unclaimed. These are suggested service rates with 0% commision upon successful connection
Industry Focus. “Computer Hardware”
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