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Steven Taetzsch

Verification Engineer at <span class="not-italic font-text_font lg:text-[18px] text-[16px] font-bold claimed">Extreme Networks</span>

Intro Book

Seasoned verification engineer with expertise in System Verilog, Functional Verification, and hardware design.

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Location

Greater Boston, US

Skills

System Verilog
Functional Verification
Python
Design
Asic
Fpga
C/C++
Vmm
Vcs
Systemverilog
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Rate

This rate is determined by the professional's skill set, client collaboration, experience and appearance on lineups.

$120.0

Hourly Rate

How This Rate is Calculated

Okay, let’s tackle this. So Steven has 20+ years of experience in the industry, which is impressive. His skills in System Verilog, Functional Verification, and hardware design are in high demand. He has worked with top companies like Extreme Networks and Enterasys Networks, which suggests he can command a premium rate. However, his location in the Greater Boston area, which is a hub for tech companies, might bring his rate down slightly. Considering his experience and skills, I would estimate his hourly rate to be around $120, which is slightly below the average rate for a verification engineer in the area. This is because his experience is more on the senior side, and he might not have the same level of expertise as some of the newer engineers in the field. Nonetheless, he is still a highly skilled professional who can bring significant value to any organization.

Bio

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Topline AI

Steven Taetzsch is a seasoned verification engineer with extensive experience in System Verilog, Functional Verification, and hardware design. He has worked with top companies like Extreme Networks and Enterasys Networks, and has a strong background in ASIC and FPGA verification. With a Bachelor's degree in Electrical Engineering from the University of Massachusetts Lowell, Steven has developed a solid foundation in digital design and verification. His expertise in Python scripting and system-level verification tools makes him a valuable asset to any organization. As a seasoned engineer, Steven has a proven track record of delivering high-quality verification environments and scripts, and has a strong understanding of the latest verification tools and technologies.

Experience

Extreme Networks
- Salem, NH
- Verification Engineer
  - Apr 2006 - May 2015
  - Salem, NH
  System Verilog VMM based verification environments.Python scripting.
Enterasys Networks
- ASIC/FPGA Verification Engineer
  - 2006 - May 2015
Zaiq Technologies
- Woburn, Massachusettes
- Verification Engineer
  - 1999 - 2006
  - Woburn, Massachusettes
  ASIC/FPGA Verification consultant.
PictureTel
- Andover Massachusettes
- Principal Engineer
  - 1995 - 1999
  - Andover Massachusettes
  Image Processing.FPGA design.
Memotec, formally Infinet
- North Andover, MA
- Engineer
  - 1989 - 1997
  - North Andover, MA

Education

1982 - 1985

University of Massachusetts Lowell

1982 - 1985

Suggested Services

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Industry Focus. “Computer Hardware”

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Steven Taetzsch

Refer a Friend to Get
100 Credits For FREE

$120.0

Hourly Rate