Bio
Credentials
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Computer Engineering
Polytechnic Institute of New York UniversityJan, 2010- Jun, 2026 -
Certification in VLSI Engineering
UCSC Extension Silicon Valley
Experience
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Design Engineer
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United States
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Semiconductors
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1 - 100 Employee
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Design Engineer
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Oct 2012 - Present
- Responsible for static time constraints development, synthesis, power and area optimization, scan chain insertion for MIPI M-PHY, USB2.0 PHY- Responsible for Timing Sign-off (STA) for MIPI M-PHY, D-PHY, ONFI, USB2.0 PHY- Power Analysis and Back-annotated SDF Simulations
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Design Engineering Intern
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Jun 2012 - Oct 2012
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Graduate Assistant
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Sep 2011 - Dec 2011
Responsible for VLSI design and implementation of high speed cross bars in 32nm technology.Handle responsibilities of analyzing and evaluating multi-core interconnection on the chip.Handle the tasks of maintaining and updating the documentation of complete hardware design.
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Graduate Assistant
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May 2010 - May 2011
Helped Administrative Assistants in preparing new I-20’s and DS-2019’s.Oriented International students regarding the rules of Immigration, Curricular & Optional Practical Training.
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Education
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2010 - 2012Polytechnic Institute of New York University
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2012 -UCSC Extension Silicon Valley
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2005 - 2009Visvesvaraya Technological University
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