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Siddesh Halavarthi Math Revana
Sr Dir, Engineering at QUALCOMM
Siddesh Halavarthi Math Revana is a seasoned design expert with 22 years of experience in CPU architecture, design, and verification, holding two US patents, and a Master's degree in Microelectronics from BITS Pilani.
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Location
Bengaluru, Karnataka, India, IN
Skills
- Design
Bio
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Topline AI
Siddesh Halavarthi Math Revana is a seasoned professional with expertise in CPU systems design and architecture.
He has led CPU systems design and architecture efforts at Qualcomm, resulting in the development of high-end CPU cores, clusters, and coherent interconnects.
Revana has also worked extensively on design verification of leading-edge DDR Memory Controllers, high-speed PHYs, and network interconnects, and has successfully deployed Assertion Based Verification, Formal Verification, and Coverage Convergence Techniques.
He holds a Master of Science degree in Microelectronics from Birla Institute of Technology and Science (BITS), Pilani, and a Bachelor of Engineering degree in Electronics and Communication from Bapuji Institute of Engineering and Technology.
Experience
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QUALCOMM
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Bengaluru Area, India
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Sr Dir, Engineering
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Jul 2002 - Present
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Bengaluru Area, India
CPU systems Architecture, Design, Verification and Post-Si debug leadershipCPU systems Design and Architecture which involves latest/greatest/high-end CPU cores, clusters, coherent interconnects and bunch of IPs to make the system work. Has "2" granted US patents. Experienced in CPU low...
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Velankani Information Systems
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Bangalore, India
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Design Engineer
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Dec 2000 - Jun 2002
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Bangalore, India
Design and verification of Viterbi Encoder and Decoder for 3G wireless
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Education
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Birla Institute of Technology and Science (BITS), Pilani
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Bapuji institute of engineering and technology
Suggested Services
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Industry Focus. “Telecommunications”
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