Experience

• 

  Clas-SiC Wafer Fab Ltd

  • Semiconductor Manufacturing
  • 1 - 100 Employee

  • Senior Device Scientist

    • Nov 2023 - Present

    Lead in developing and optimizing SiC MOSFETs processes and modules for development projects and improving yields. Delivering robust, well-characterized Process Design Kits. Interfacing with customers for ongoing and new projects to adapt process capabilities as per project requirements. Lead in PDK qualification and failure analysis covering 1.2K, 1.7K, and 3.3 kV SiC power MOSFETs for typical tests including TDDB, HTRB, HTGB, H3TRB, and TC.

  • Device Scientist

    • Nov 2021 - Oct 2023

    Monitoring and improving SiC power Diodes and MOSFETs yields by optimizing relevant fab processes. Data (physical/electrical) analysis to debug and robust fabrication processes. Python programming for test data analysis to track key specs trendlines, and yields of various device types.

• 

  UCL

  • London, England, United Kingdom

  • Research Fellow

    • Mar 2020 - Oct 2021
    • London, England, United Kingdom

    Low-Dimensional (1D/2D) Quantum Transport in GaAs-based systems

• 

  Sungkyunkwan University

  • Construction
  • 700 & Above Employee

  • Research Professor, Korea Research Fellow, PI

    • Sep 2015 - Feb 2020

    Guided Masters and graduate students in their research projects, the research focus area includes: • Graphene Oxide-MoS2 hybrid, active three terminal gas sensors• Klein Tunneling in graphene and future device architecture based on 2D materials

  • Research Professor, Brain Korea (BK-21)

    • Aug 2014 - Aug 2015

    • Graphene oxide nanoparticles hybrid for proficient gas sensing• Fabrication and characterization of Graphene-MoS2 FETs and diodes• Development of Graphene Oxide and TMDs based NDR devices

  • Post-Doctoral Fellow in World Class University (WCU) project

    • May 2012 - Jul 2014

    • Experimental Investigation and COMSOL Multiphysics Simulation of switching mechanism and role of thermal effects in electric field induced resistive switching in VO2 nanowires and thin-films• Development of Memristors, resistive memories, based on VO2 Thin Films

• 

  Indian Institute of Technology, Kharagpur

  • Kharagpur, India

  • Senior Research Fellow, Post-PhD

    • May 2011 - Apr 2012
    • Kharagpur, India

    • Impact of aspect ratio on the logic performance of strained InGaAs HEMTs• Thermal simulation of InAlN/AlN/GaN on Si based HEMTs• State-of-Art Riber C-12 MBE grown AlGaAs/InGaAs PHEMTs on GaAs substrate are fabricated and characterized viva Hall, PL, ECV, probe method etc, for various indium composition and thickness of channel. The In composition-dependent critical thickness and effect on Idmax, gm etc are also analyzed with TCAD simulations.

• 

  University of Delhi, South Campus

  • India
  • Higher Education
  • 700 & Above Employee

  • Senior Research Fellow, CSIR

    • Mar 2011 - Apr 2011

    Modeling and optimization of T-Gate for accurate analysis and effect on device performance.

  • Senior Research Fellow

    • Apr 2010 - Feb 2011

    Composite-channel (InGaAs/InP/InGaAs) HEMTs with double gate control are analysed for improved breakdown voltage and consistent RF performance. Various gate-geometries, realized as field-plates are also analyzed through TCAD simulation considering variation in gate resistance and channel field for the best combination of enhanced breakdown voltage and RF performance.

  • Junior Research Fellow

    • Jan 2008 - Mar 2010

    • Develop a Physical Model to account for the parasitic resistances and capacitances of T-Gate geometry in HEMTs and its implementation as Field Plates.• Carried out channel thickness optimization (10-80 nm) to mitigate SCEs for improved RF and switching performance in both Single- and Double- Gate HEMTs.• Proposed Charge based Physical Model for separated Double- Gate HEMTs.