Bio
Experience
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Vanguard International Semiconductor Company
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1 Tampines, Industrial Avenue 5, Singapore
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Principal Member Of Technical Staff, MEMS-R&D
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Jan 2020 - Present
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1 Tampines, Industrial Avenue 5, Singapore
My present responsibilities include:1. As MEMS Project Director, responsible for managing projects during the project life cycle2. Manage MEMS Technology Development and Process Integration3. Manage Technology Qualification and Transfer for manufacturing4. New Customer Engagement from project proposal till project approval5. Drive MEMS technology innovation and new capability development
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GLOBALFOUNDRIES
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1 Tampines, Industrial Avenue 5, Singapore
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Principal MTS/Deputy Director - MEMS-TD
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Apr 2012 - Dec 2019
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1 Tampines, Industrial Avenue 5, Singapore
My responsibilities included:1. Project Management of Piezoelectric MEMS Projects during the project life cycle.2. Responsible for Piezoelectric MEMS Technology Development and Process Integration 3. New Customer Engagement from project feasibility review till project approval4. Chairman of MEMS Process Change Management Board5. MEMS Research collaborations with Research Institutes and MEMS Consortia.
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MEMS Process Technology Manager
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Oct 1998 - Mar 2012
- Responsible for MEMS and Wafer level packaging technology development- Manage internal MEMS Research and Industry Projects- Roadmapping and spearheading new capability development for emerging applications- Experienced in Piezoelectric, Intertial, Optical, Microfluidic and Microphone technologies- Training and Manpower development for MEMS Industry in Singapore
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Bharat Heavy Electricals Limited
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Haridwar, India
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Manager (ASIC wafer fab)
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Apr 1990 - Oct 1995
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Haridwar, India
- Responsible for ASIC back-end of the line (BEOL) wafer fabrication facility - Manage Procurement and process start-up for the BEOL Semiconductor Wafer Fab.- Responsible for Module development & BEOL integration- Manage routine operations and upkeep of the wafer fab
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Semi-Conductor Laboratory (SCL)
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Sector 72, S.A.S Nagar - 160 071 Punjab, India.
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Member of Technology Development Team (R&D)
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Aug 1984 - Apr 1990
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Sector 72, S.A.S Nagar - 160 071 Punjab, India.
- Responsible for Plasma Etch Process Module in R&D Fab- Development of etch modules for 3µm/1.25µm CMOS technology for low/high voltage application- Responsible for procurement and start-up of etch tools for R&D fab.
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Education
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2004 - 2010Nanyang Technological University
PhD, Electronics and Electrical Engineering -
1982 - 1984Indian Institute of Technology, Delhi
M.Tech, Integrated Electronics and Circuits -
1977 - 1982Osmania University
B.E, Electronics and Communication Engineering (ECE)
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