Experience

• 

  Ventana Micro Systems

  • United States
  • Computer Hardware Manufacturing
  • 1 - 100 Employee

  • Post Silicon Validation Engineer

    • Jul 2022 - Present

    New journey with RISC-V.

  • Post Silicon Validation Engineer

    • Jul 2022 - Present

    New journey with RISC-V.

  • Post Silicon Validation Engineer

    • Jul 2022 - Present

    New journey with RISC-V.

• 

  Wipro

  • Senior Project Engineer

    • Jun 2021 - Jul 2022

  • Project Engineer

    • Feb 2019 - Jan 2022

    • Extensive experience as a Power Management Post Silicon Validation and Triage Engineer of Intel Platforms.• Responsible for driving quality on the power management features across Intel platforms, triaging issues, and disposition to relevant HW/FW/SW components.• Working knowledge of CPU, and system architectures and their implications on system power and performance.• Basic knowledge on OSPM, ACPI defined states, System sleep states, Device states.• Responsible for Platform System bring-up, Post Si-validation, and triage of failures.• Responsible for triaging Caterror, System Hard and Soft Hang, device enumeration, yellow bang, System low power states related issues.• Hands-on Experience to triage SOC-related failure by analyzing ITP, hang dumps, ACPI logs capture, capturing and analyzing Software Event, Sleep Study, and Socwatch Logs.• Knowledge of Validation/Triage Flows of Power Management Functional and Stress & Stability.• Work with Intel's ingredient, system validation, and Microsoft-facing teams to fit all the pieces together and track the bugs to closure.• Demonstrated experience giving junior engineers technical direction on issues and daily tasks based on program priorities.• Responsibilities include client interaction daily.