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Lalit Gangwar

DFT & Physical Design Engineer at Tecquire Solutions Pvt Ltd
Intro Book
Lalit Gangwar, a seasoned engineer with 1 year 4 months of experience, holds a Bachelor's degree in Electrical, Electronics and Communications Engineering from Gautam Buddha University, proficient in English and Hindi, and skilled in DFT, Physical Design, ATPG, and more.
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Location
Uttar Pradesh, India, IN
Languages
  • English Full professional proficiency
  • Hindi Full professional proficiency
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Credentials

  • Innovus Implementation System (Block) v23.1 Exam
    Cadence Design Systems
    Mar, 2024
    - Apr, 2026
  • Cadence RTL-to-GDSII Flow v5.0 Exam
    Cadence Design Systems
    Feb, 2024
    - Apr, 2026
  • Innovus Implementation System (Block) v22.1 Exam
    Cadence Design Systems
    Feb, 2024
    - Apr, 2026
  • Basic Static Timing Analysis v3.0 Exam
    Cadence Design Systems
    Jan, 2024
    - Apr, 2026
  • Design for Test Fundamentals v4.0 Exam
    Cadence Design Systems
    Jan, 2024
    - Apr, 2026
  • Semiconductor 101 v1.0 Exam
    Cadence Design Systems
    Jan, 2024
    - Apr, 2026
  • Verilog Language and Application v26.0 Exam
    Cadence Design Systems
    Jan, 2024
    - Apr, 2026
  • Tessent Integrated Flow - v22.16
    Siemens Digital Industries Software
    Nov, 2023
    - Apr, 2026
  • Tessent MemoryBIST - v22.16
    Siemens Digital Industries Software
    Oct, 2023
    - Apr, 2026
  • Tessent Scan and ATPG - v22.16
    Siemens Digital Industries Software
    Oct, 2023
    - Apr, 2026
  • Tessent Shell Automation - v22.16
    Siemens Digital Industries Software
    Oct, 2023
    - Apr, 2026

Experience

  • Tecquire Solutions Pvt Ltd
    • Noida, Uttar Pradesh, India
    • DFT & Physical Design Engineer
      • Mar 2023 - Present
      • Noida, Uttar Pradesh, India

      - Responsible for Floor Planning, Placement, CTS, Routing, and Sign off.- Responsible for block level Memory BIST Testing.- Responsible for block level Scan, EDT, OCC Insertion.- in-depth knowledge of RTL to GDS flow- in-depth knowledge of Physical design concept.- In-depth Knowledge of ATPG, MBIST Pattern Generation & Simulation.

  • NRS Design Technology
    • Greater Noida, Uttar Pradesh
    • Design Verification Intern
      • Sep 2022 - Feb 2023
      • Greater Noida, Uttar Pradesh

      -Worked as a Design Verification Intern.-Design System Verilog Environment for Memory Circuitry.-Design UVM Environment for Combinational Circuitry.

  • Omnipresent Robot Tech
    • Greater Noida, Uttar Pradesh
    • Engineering Intern
      • Jun 2022 - Jul 2022
      • Greater Noida, Uttar Pradesh

      - Worked as a PCB design engineer- Responsible Designing PCB for Battery management system

Education

  • 2019 - 2023
    Gautam Buddha University
    Bachelor's degree, Electrical, Electronics and Communications Engineering

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