Experience

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  MediaTek

  • Austin, Texas Area

  • Circuit Designer

    • 2013 - Present
    • Austin, Texas Area

    - Design and verify digital and mixed-signal custom circuits to meet the power, performance and area requirements for multiple technology nodes. Circuits include: Power Switch, Power Retention Circuit, Leakage Sensor, Clock-Tree Buffers and Duty Cycle Corrector- Own IPs for the entire design process, including: schematic capture, pre-layout simulations, floorplanning, post layout verification, and final IP release for these IPs- Analyzed standard library cells to improve speed while reducing power and area- Drove efforts in metal stack benchmarking for two technology nodes

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  IBM

  • ASIC Application Engineer

    • 2007 - 2013

    - Worked on ASIC chips in 90nm, 65nm,45mn and 32nm technologies with extensive experience in chip level power estimation using the IBM power spreadsheet and power tools. - Solved customer issues such as tools, methodology, IP's and IP/library releases process. Work closely with development teams to investigate problems seen in customer environment and promptly provided resolution to minimize design impact.- Provided global support to customers in China, Japan and France. My fluency in Chinese enabled efficient communication to key customers in China reducing miscommunication and response time. - Supported the 3rd party USB core and lead efforts to ensure all IBM designs using this core had the correction configuration settings, acceptable simulation results and proper usage to achieve first time right.

  • Physical Design

    • 2010 - 2011

    - Built RLMs in 45nm technology – Analyzed efficient placement options using the IBM PDS tool (time-driven placement), inserted clock trees, performed routing and congestion analysis, resolved DRC / LVS issues, ran statistical timing analysis and closed timing on RLMs.- Floorplanning ~50um2 ASIC – Placed functional units, assigned ports for optimal routing, and placed chip IOs and small logic blocks; used Cadence Space Based Router for wire analysis.

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  IBM

  • Austin, TX

  • Verification and Model Build

    • 2008 - 2009
    • Austin, TX

    - Performed verification debug using the Verdi Waveform viewer. - Responsible for generating tests, running regressions, and verifying the model build process.

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  IBM

  • Austin, TX

  • Circuit Design

    • 2004 - 2007
    • Austin, TX

    Worked on array and custom circuit designs for the Cell Processor. ARRAY DESIGN- Used Spice simulator to optimize, verify and analyze 45nm 6T SRAM array designs; - Performed layout, DRC, LVS and methodology checks on 6T SRAM array.- Analyzed array timing and functionality using IBM Spice simulation tool.- Resolve layout and timing tool problems and provided input for tool enhancements to EDA team.CUSTOM CIRCUIT DESIGN - Designed and verified custom circuits for Cell Processor (65nm and 45 nm) in the synergistic processing unit and core unit (execution and memory); - Designed and simulated cross sections for timing critical paths.- Knowledgeable in RTL. Verified core unit and macro schematics versus VHDL equality and analyzed failed logic cones using equivalence checking tool. - Worked on layout verification, DRC, LVS, physical block layout and schematic migration from 65nm to 45nm.- Analyzed and performed IR/EM (IR drop/Electromigration) and noise simulations on multiple core units of the chip.

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  Intel Corporation

  • Hillsboro, Oregon

  • Summer Intern in Microprocessor Design Group (2001,2002 and 2003)

    • May 2001 - Aug 2003
    • Hillsboro, Oregon

    - Performed timing analysis, implemented power saving methods, ran simulation/characterization flows for library cells used in Pentium IV.

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  Avnet

  • Phoenix, Arizona Area

  • Co-op in Design Services Division

    • Dec 2000 - May 2001
    • Phoenix, Arizona Area

    - Designed schematics for PCI board with Virtex II demonstrating DSP functionalities (speech shifting/recording)

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  Hewlett-Packard

  • Roseville, California

  • Product Engineering Intern

    • May 2000 - Aug 2000
    • Roseville, California

    - Developed a web-based high-end server debug guide for manufacturing and support logistics operations.and assisted test engineering in system level troubleshooting activities for the high-end server.