Topline | Janarthanan (Gt) Gilari

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Janarthanan (Gt) Gilari

Principal Engineer at <span class="not-italic font-text_font lg:text-[18px] text-[16px] font-bold claimed">Intel Corporation</span>

Intro Book

Experienced engineer with expertise in SOC/ASIC Design Verification and computer hardware.

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Location

Austin, Texas, United States, US

Skills

Design
Components
Research
Technology
Soc
Computer Hardware
Mask
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Rate

This rate is determined by the professional's skill set, client collaboration, experience and appearance on lineups.

$275.0

Hourly Rate

How This Rate is Calculated

Okay, let’s tackle this. So Janarthanan has 22 years of experience as a Principal Engineer at Intel Corporation, with expertise in SOC/ASIC Design Verification. He also worked at Motorola for 1.5 years. His education from reputable institutions like The University of Texas at El Paso and National Institute of Technology, Tiruchirappalli adds to his credibility. Skills like SOC/ASIC Design Verification, PowerPC cluster verification, and computer hardware are in demand. Location is Austin, Texas, which is a hub for tech companies. Engineers with his level of experience, especially in hardware and verification, typically charge higher rates. Maybe around $250–$400 per hour? But considering his leadership role at Intel and education from top universities, maybe higher. Some top engineers in the industry can charge $500+. Let’s check averages. Engineers with his background might average $300–$450. So I’ll estimate around $325–$375, but since I have to choose one, I’ll go with $275

Bio

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Topline AI

Janarthanan (gt) Gilari is a seasoned engineer with expertise in SOC/ASIC Design Verification, PowerPC cluster verification, and computer hardware. He has led design verification at Intel Corporation and worked at Motorola. He holds a Master of Science in Computer Engineering and a Bachelor of Engineering in Electrical and Electronics Engineering.

Experience

Intel Corporation
- Austin, Texas
- Principal Engineer
  - Dec 2001 - Present
  - Austin, Texas
  SOC/ASIC Design Verification leadExpertise in reset, boot and power management architecture, uarch and verification.
Motorola
- Austin, Texas
- Design Verification Engineer
  - Aug 2000 - Dec 2001
  - Austin, Texas
  PowerPC - Somerset Design Center. Cluster verification using C++ TB

Education

The University of Texas at El Paso
National Institute of Technology, Tiruchirappalli

Suggested Services

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Industry Focus. “Computer Hardware”

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Janarthanan (Gt) Gilari

Refer a Friend to Get
100 Credits For FREE

$275.0

Hourly Rate