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James Su is a seasoned semiconductor professional with 12+ years of experience in low power design, hierarchical design, and clock domain crossing. He holds a Master's degree in Computer Science from National Chung Cheng University and a Bachelor's degree in Computer Science from National Chiao Tung University. He has worked at leading companies like MediaTek, TSMC, and Faraday, where he has developed expertise in power domain design, unified low power design verification flow, and synthesis and CTS design rule and verification flow development.

Experience

  • Rivos Inc.
    • 台灣 Taiwan 新竹縣
    • CPU Implementation
      • Jan 2023 - Present
      • 台灣 Taiwan 新竹縣

  • MediaTek
    • Hsinchu County/City, Taiwan
    • Senior Manager
      • Mar 2010 - Dec 2022
      • Hsinchu County/City, Taiwan

      Large scale hierarchical low power implementation and flow development.Defined power domain design rule and constructed unified low power design verification flow from Design, Simulation, APR and Conformal-Low Power, that supports CPF and UPF based EDA tools.Synthesis and CTS design rule and verification flow development.Served as project top integrator, project leader and manager for real-time flow development and tape-outTaskforce Lead -New Process Node development in TSMC cutting edge Nodes. Worked as coordinator in collaboration with internal functions teams across synthesis, APR, Sign-off and library kits. as well as contact with foundry. -Full Flow Consolidation of solutions across integration, synthesis and APR technology to overcome new process node challenge and shorten turn-around-time. -PD SoC Project tape-outs of products in SmartPhone, Tablet, TV and BlueRayOperational Events -Manager of PD Project, CAD team in Synthesis, APR, CTS, UPF verification. -Cross country management in Taiwan and Singapore

  • TSMC
    • Hsinchu County/City, Taiwan
    • Principle Engineer
      • Sep 2009 - Mar 2010
      • Hsinchu County/City, Taiwan

      T40 customer engagement by composing TCD cell insertion and checker of Encounter/ICC/Magma and power mesh improvement for more 20 percent routing resource.Reference flow 11.0: collaboration with EDA RD on low power implementation and verification topics.

    • Deputy Manager
      • Aug 2002 - Sep 2009

      Created and managed Encounter, Virtusuo, Pin assign and GDS utilities using TCL, C and SKILL language.Delivered course as oversea agent training, physical design flow, UMC 0.13um process and low power design flow.Served for real-time flow development and multiple project tape-outs.Support San Jose office in 2014/Q4, 2005/Q3, 2006/June, 2007/Q4 for large scale low power and hierarchical projects and customer engagement.

Education

  • 2000 - 2002
    National Chung Cheng University
    Master, Computer Science
  • 1996 - 2000
    National Chiao Tung University
    Bachelor, Computer Science

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Industry Focus. “Computer Hardware Manufacturing”

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