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Ivana Vasiljević profile image

Ivana Vasiljević

Analog Mixed-Signal Design and Verification Engineer at ELSYS Eastern Europe
Intro Book
Ivana Vasiljević, a seasoned Analog Mixed-Signal Design and Verification Engineer with 5+ years of experience, holds a Doctor of Philosophy degree from University of Belgrade, with expertise in SystemVerilog, Verilog, and Cadence tools.
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Location
Serbia, RS
Languages
  • English Professional working proficiency
  • Serbian Native or bilingual proficiency
  • French Elementary proficiency
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Experience

  • ELSYS Eastern Europe
    • Serbia
    • Analog Mixed-Signal Design and Verification Engineer
      • Feb 2019 - Present
      • Serbia

      Working as contractor for leading semiconductor automotive company.Modeling:- Design of WREAL/VAMS models according to schematics and specifications- Matching model vs schematics- Integration in top levelTop level mixed-signal verification:- Writing tests regarding test cases specification- Running and debugging simulation- Analyzing and improving toggle coverageDigital verification:- Running and debugging regression- IP coverage closure (writing tests, basic UVC componentdevelopment)- Aligned Makefile and vsif files for IPs (migration to Xcelium, easymaintenance)Methodology: UVMTools: Cadence (Virtuoso, SimVision, ADE-L), vManager, DesignSyncPrograming languages: SystemVerilog, VerilogAMS

Education

  • 2019 -
    University of Belgrade, Faculty of Electrical Engineering
    Doctor of Philosophy - PhD
  • 2018 - 2019
    University of Belgrade, Faculty of Electrical Engineering
    Master of Science (MSc), Electronics
  • 2014 - 2018
    University of Belgrade, Faculty of Electrical Engineering
    Bachelor of Science (BSc), Electronics, Electrical and Electronics Engineering
  • 2010 - 2014
    High School "Vuk Karadžić", Loznica

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Industry Focus. “Semiconductor Manufacturing”

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