Bio
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Experience
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Chief Architect and Co-Founder
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Mar 2022 - Present
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ASIC design group manager and technical lead
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Feb 2017 - Mar 2022
Manager of two design teams and owner of ASIC development methodologiesResponsible for Arch, uArch, coding, verification, and execution of ASIC units.
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United States
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Semiconductor Manufacturing
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700 & Above Employee
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FPGA team Technical Lead
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Oct 2014 - Feb 2017
Technical leading of FPGA team. Responsible for FPGA micro-architecture, design methodologies, BE methodologies and CAD.
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Dynamic verification engineer
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May 2013 - Nov 2014
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FPGA and Logic designer
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Sep 2010 - May 2013
Part of a hardware imaging team, specializing in logic and board design of cameras for airborne systems.Designed and implemented on FPGAs image processing algorithms, interface units, controllers and full top level chip.
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Education
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2009 - 2013Technion-Machon Technologi Le' Israel
Bachelor of Science (BSc), Electrical and Electronics Engineering -
2013 -Technion - Israel Institute of Technology
Master of Science (MS), Computer Architecture
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Industry Focus. “Data Infrastructure and Analytics”
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