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Experience

    • Chief Architect and Co-Founder
      • Mar 2022 - Present

    • ASIC design group manager and technical lead
      • Feb 2017 - Mar 2022

      Manager of two design teams and owner of ASIC development methodologiesResponsible for Arch, uArch, coding, verification, and execution of ASIC units.

    • United States
    • Semiconductor Manufacturing
    • 700 & Above Employee
    • FPGA team Technical Lead
      • Oct 2014 - Feb 2017

      Technical leading of FPGA team. Responsible for FPGA micro-architecture, design methodologies, BE methodologies and CAD.

    • Dynamic verification engineer
      • May 2013 - Nov 2014

    • FPGA and Logic designer
      • Sep 2010 - May 2013

      Part of a hardware imaging team, specializing in logic and board design of cameras for airborne systems.Designed and implemented on FPGAs image processing algorithms, interface units, controllers and full top level chip.

Education

  • 2009 - 2013
    Technion-Machon Technologi Le' Israel
    Bachelor of Science (BSc), Electrical and Electronics Engineering
  • 2013 -
    Technion - Israel Institute of Technology
    Master of Science (MS), Computer Architecture

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Industry Focus. “Data Infrastructure and Analytics”

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