Bio
Experience
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Physical Back End Designer
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Sep 2009 - Present
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Staff engineer (P&R)
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Aug 2000 - Feb 2009
• Responsible for physical layout for large digital block designs from 10-15M gates using TSMC130 or TSMC090 um technologies. Usually, assigned to work on 3 to 5 blocks because my manager knew that I can deliver good quality results, on-schedule, and works first time.• Significant expertise in IC...
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Staff Engineer / Place & Route
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2000 - 2009
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Senior engineer
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Apr 1995 - Aug 2000
• Used Cadence Gate Ensemble to perform physical placement and routing of ASIC designs with IBM C5L 0.5 um technology and applied Preview Floor planner to optimize macro placements• Performed design verification using Cadence Dracula tools• Involved in several ASIC designs doing floor planning, ...
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Senior engineer
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Feb 1978 - May 1995
• Installed, evaluated, and tested Motorola OACS (Open Architecture CAD System) design system in different platforms such as Apollo, SUN, and HP• Released OACS tools and libraries to Unisys internal users and system plants• Actively involved in the physical verifications of modified versions of C...
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Electrical and Instrumentation Mechanic
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Jul 1973 - Aug 1977
Skilled technician in one of the largest fertilizer and chemical process plants in Asia.Installed, calibrated, and trouble shot electrical/pneumatic instruments, e.g., flow meters, level transmitters, temperature controllers, thermocouples, pressure control valves, pressure gauges, etc.Troublesho...
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Education
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1968 - 1973Mapua Institute of Technology
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Palomar College
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