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Dan Mumford is a seasoned digital circuit designer with 16 years of experience in low power design, logic design, and Verilog. He has worked at Marvell Semiconductor and Analog Devices, managing design teams and overseeing projects from specification development to silicon debug. Dan holds a Master of Engineering degree from Cornell University and a Bachelor of Science degree in Electrical and Electronics Engineering.

Experience

    • Senior Design Engineering Manager and Principal Engineer
      • Oct 1998 - Oct 2014

      -Designed high-speed/low-power circuits for technologies ranging from 0.18 micron to 16nm for multiple applications, including: Magnetic and optical storage, Gigabit Ethernet (802.3), SerDes, serial ATA, FM Radio, and GPS.-Designed high-speed data-path circuits such as digital filters, Viterbi algorithm, timing/gain recovery, fractional dividers for phase-locked loops (PLL), CORDICs, AMBA (AHB/APB)-Managed tape-outs of stand-alone hard disk drive (HDD) read channel products, as well as GDS deliveries of numerous IP cores for multiple high-volume production SOCs.-Managed a design team of six engineers.-Design responsibilities included: Specification development, architecture definition, circuit conceptualization and implementation, synthesis, functional verification, timing closure (STA), clock analysis (CDC), power analysis, design-for-test (DFT), floorplanning, supervision of physical design and place-and-route, ECOs, and signoff procedures.-Support roles included: Post-silicon validation (chip bring-up, lab evaluation, production testing) and customer documentation.-Customer interactions included: Product feature development, support for design development (including Cadence Palladium model), support for silicon evaluation and debug, leading external design reviews, documentation.

    • Design Engineer
      • Mar 1992 - Mar 1998

      ADSP-21xx fixed-point DSP microprocessorsResponsibilities included:-Custom schematic-entry design-Functional verification-Simulation environment for IKOS hardware emulator-Pathmill & SPICE timing analysis-Floorplanning-Supervision of physical layout-LVS/DRC verification and DRACULA flow development-Tapeout formalities-Silicon debug-Customer application issuesSelect list of design projects:-Instruction Fetch and Decode-Data Address Generation-ALU/Multiplier/Barrel Shifter-Delay-locked loop (DLL)-On-chip SRAM-Schmitt trigger-Serial port interface-DMA port-JTAG interface

    • Volunteer Telephone Counselor
      • 1907 - 1915

      Correction: 2007-2015 (8 years)Telephone Counselor for Contact Cares Community Helpline

Education

  • Cornell University
    Master of Engineering (MEng), Electrical and Electronics Engineering
  • Cornell University
    Bachelor of Science (BS), Electrical and Electronics Engineering
  • Mission College
    Communications Studies Certificate of Proficiency

Suggested Services

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Industry Focus. “Computer Hardware”

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