Experience

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  Nantero

  • Woburn, MA

  • Nantero Fellow

    • Jan 2003 - Present
    • Woburn, MA

    Nantero Fellow, Carbon Nanotube R&DNantero, Inc., Woburn, MA. (Jan. 2003-Present)• Development of carbon nanotube-based nonvolatile resistive devices designed to operate as storage devices in memory arrays with cells also including MOSFET or diode select devices for standalone and embedded memory applications, as well as carbon nanotube cross point arrays for maximum density, and integration in CMOS fabricators.• Development of carbon nanotube logic devices (CNTFETs) and circuits, including combinations of CMOS and carbon nanotube devices for hybrid CMOS-carbon nanotube logic arrays. Also, development of carbon nanotube resistors, electromechanical switches, and sensors. • Carbon nanotube intellectual property development and patent filings in support of Nantero business objective resulting in 300 issued US patents.

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  Bertin Consulting

  • S. Burlington, VT

  • Consultant

    • Mar 2000 - Jan 2003
    • S. Burlington, VT

    • Expert Witness in Mosel Vitelic vs. Hitachi for Morgan, Lewis, & Bockius LLP Law Firm. Patent analysis in support of Hitachi. • Expert Witness in Hyundai vs. Rambus for Simmons & Simmons Law Firm, UK. Patent analysis in support of Hyndai.

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  IBM

  • Burlington, Vermont Area

  • Senior Technical Staff Member and Manager

    • 1970 - Mar 2000
    • Burlington, Vermont Area

    • 1996-2000: DRAM Alliance. IBM, Infineon (Siemens), & Toshiba (STSM/Manager). Manager of IBM 256 Megabit SDRAM design team. The chip design and fabrication was carried out in 0.15 um CMOS DRAM technology. • 1991-1995: Development of 3-D Memory (STSM/Lead Engineer).640 Megabit DRAM product/technology development for mainframes and radiation hardened space recorders, including redundancy and error correction. The 640 Megabit DRAM formed with 40 laminated 16 Megabit DRAM chips.The 640 Megabit DRAM memory cube is illustrated and described in Book Chapter 4 by C. Bertin et al., “Known Good Die (KGD)”, in “Area Array Interconnection Handbook”, editors K. Puttlitz & P. Totta, published 2001 by Kluwer Academic Publishers. • 1987-1990: Early Development of 64 Megabit DRAM Product (STSM/Manager).Defined product and technology requirements for 0.35 um 64 Megabit DRAM product. One of four members of an IBM team that negotiated a large multi-million dollar contract between IBM and Siemens for joint development and fabrication of 64 Megabit DRAM in IBM facilities in NY and VT. • 1982-1986: High-Performance Static RAM Development and Qualification (Sr. Eng./ Manager).Managed development and qualification of a high-performance 1 Megabit Static RAM (SRAM), designed and fabricated at the 0.8 um CMOS technology node, and described in an ISSCC 1988 paper. Also, developed and qualified the first IBM SRAM CMOS macros for a CMOS ASIC logic family at a technology node of 1.0 um.• 1970-1982: NMOS Device Development. NMOS Logic Development, Qualification, & Manufacturing (Associate Eng.-to-Sr. Eng./Manager). Team leader for first NMOS logic family in IBM at a technology node of 5 um. Then, managed 50 people responsible for ASIC logic product design, qualification, and release to manufacturing at 3.0 and 1.5 um technology nodes. Logic products were manufactured in IBM fabricators in the U.S. and France.