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Chip Laub
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- Design Automation
- Semiconductors
- Design
- Optimization
- Asic
- Show all
Bio
Experience
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Asic Rtl-Gds Design Automation
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ASIC RTL-GDS Design Automation
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2009 - Present
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Product Engineering, Front-End Synthesis
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2007 - 2008
(CAE) Logic synthesis tool evaluation and benchmarking to define flow and algorithm improvements to improve timing and area result quality. Very close collaboration with R&D.
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Processor Design Engineering / CAD
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1981 - 2007
Group lead responsible for methodology and implementation for synthesis, place and route for modules of several major processors, to 45nm. Benchmarking of candidate CAD tools. Cross-site standardization of standard-cell approaches for processor projects. Previous work in mixed-signal componen...
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Education
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1976 - 1977Stanford University
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1972 - 1976
Massachusetts Institute of Technology
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Industry Focus. “Semiconductors”
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