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Cheng-tao Hsieh is a seasoned technical professional with a strong background in computer science and engineering. He has extensive experience in design verification, machine learning, and chip architecture, having worked at top companies such as Qualcomm and Atheros Communications. He holds a PhD in Computer Science from National Tsing Hua University and has completed various certifications in machine learning and logic. He has been involved in numerous high-profile projects, including the development of verification plans for complex chip designs and the analysis of power consumption using static analysis techniques. As a technical lead at a startup, he has been responsible for designing and developing image processing algorithms, machine learning models, and cloud computing systems. Hsieh has also published research papers on low power strategy for sensors and clock tree optimization for timing closure. He is proficient in a range of programming languages, including C, C++, and Python, and has experience with various verification tools such as Vera, SystemVerilog, and UPF. With his unique blend of technical expertise and industry experience, Hsieh is well-equipped to tackle complex technical challenges and drive innovation in the field of computer science and engineering.

Credentials

  • Machine Learning
    Coursera
    Sep, 2014
    - May, 2026
  • Introduction to Logic
    Coursera
    May, 2013
    - May, 2026

Experience

    • Technical Lead
      • 2015 - Present
      • Taiwan

      Be responsible for* Image processing algorithms* machine learning* cloud computing

  • Qualcomm
    • Taiwan
    • Design Verification Engineer
      • 2011 - 2015
      • Taiwan

      Atheros was acquired by Qualcomm at 2011.Qualcomm is really a big company owning several RD centers around the world. Here I learned to co-work with people in different time zones to finish a complex project. Also Qualcomm encourages every employee to develop themselves and invent new things. So ...

    • Design Verification Engineer
      • 2007 - 2011
      • Taiwan

      The earlier you catch bugs, the less you spend to fix. My job was to catch bugs in the early (RTL) stage of designing IC. It is not easy. Nowadays chips can pack tons of modules within a tiny area, so called System-on-a-chip. So many functions are activated at the same time, so it’s becoming diff...

  • Faraday
    • Taiwan
    • Intern -- Design Flow Engineer
      • 2001 - 2001
      • Taiwan

      Studied the IR drop problem and developed a Software to analyze it.

Education

  • 2002 - 2007
    National Tsing Hua University
  • 2006 - 2006
    UCLA
  • 2000 - 2002
    National Chung Cheng University
  • 1996 - 2000
    National Chiao Tung University

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