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Bob Bechdolt profile image

Bob Bechdolt

Staff Yield Engineer at Microchip Technology Inc.
Intro Book
Seasoned semiconductor professional with 26+ years of experience in device modeling, process integration, and yield improvement.
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Location
San Francisco Bay Area, US
Skills
  • Ic
  • Semiconductors
  • Cmos
  • Semiconductor Industry
  • Analog
  • Show all
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Bio

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Bob Bechdolt is a seasoned semiconductor professional with 26+ years of experience in device modeling, process integration, and yield improvement. He has held various roles at top companies, including Microchip Technology Inc., Micrel Semiconductor, Synergy Semiconductor, Digital Equipment Corp, Trilogy, and Fairchild Semiconductor. With a Master's degree from Massachusetts Institute of Technology, Bob has developed expertise in CMOS, Bipolar, and Analog circuit design, as well as semiconductor industry trends and technology projections.

Experience

  • Microchip Technology Inc.
    • Staff Yield Engineer
      • Mar 2016 - Present

  • Micrel Semiconductor
    • San Jose, CA
    • Staff Device Development Integration Engineer
      • 1998 - Present
      • San Jose, CA

      High Speed SiGe Bipolar and BiCmos Process IntegrationDevice Characterization and Modeling - FET Drivers, CMOS, Bipolar, InterconnectYield ImprovementQuality ImprovementDesign rule and DRCFoundry EvaluationManaged Modeling Engineer

  • Synergy Semiconductor
    • Santa Clara, CA
    • Device Modeling Manager
      • 1991 - 1998
      • Santa Clara, CA

      Managed PHD Senior Staff Engineer0.8um BiCmos and 1.2um Bipolar device modeling and process developmentIntegration of models into Cadence Design environmentTechnology performance projectionsTest chip design and parametric test program developmentDesign Rules and DRC programming in CadenceInterface to internal and external design groups

  • Digital Equipment Corp
    • Cupertino
    • Consulting Engineer
      • 1985 - 1991
      • Cupertino

      Characterization and Device modeling for Bipolar memory and logic circuitsProcess optimizationTransmission line characterizationManaged foundry interfaceTechnology projectionsManaged 3 engineers and a technician

  • Trilogy
    • Cupertino, Ca
    • Project Leader,Product Development; Project Leader, Device Modeling
      • 1983 - 1986
      • Cupertino, Ca

  • Fairchild Semiconductor
    • Milpitas, CA
    • Senior Design Engineer; Staff Process Engineer
      • 1977 - 1983
      • Milpitas, CA

Education

  • Massachusetts Institute of Technology
    Master's degree, Electrical Engineering
  • Massachusetts Institute of Technology
    Bachelors and Master of Science, Electrical Engineering/Solid State Physics

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Industry Focus. “Semiconductors”

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