Experience

• 

  Lightmatter

  • Senior Staff Product Test Engineer

    • Dec 2023 - Present

• 

  AMD

  • San Francisco Bay Area

  • Senior Member of Technical Staff, AECG

    • Apr 2022 - Jul 2023
    • San Francisco Bay Area

    -Evaluated latest Advantest Verigy tester platform for suitability with AMD/Xilinx current and future SoC products.-Created, supported and maintained Final Test and QA programs for Versal Premium used in AI, DSP, and data center applications.

• 

  Xilinx

  • United States
  • Semiconductor Manufacturing
  • 700 & Above Employee

  • Senior Staff Test Engineer, FPGA

    • 2012 - 2022

    -Created, supported and maintained Final Test and QA programs for: Versal AI Core/Edge, Prime, Premium, and HBM families used in AI, machine learning, and data centers UltraScale and UltraScale+ Atrix, Kintex, and Virtex families used in IC simulation, DSP, and compute intensive applications.-Maintained and upgraded virtual/offline tester simulators to enable program development and valuations saving expensive ATE resources.

  • Staff Test Engineer, FPGA

    • 2002 - 2012

    -Created, supported, and maintained Final Test and QA programs for: Artix7, Kintex7, Zynq7, Virtex6, Virtex5, Virtex4, and Virtex2PRO families-Created specialized test methodology and patterns to verify die-bonding and package-pin contact with the innovative shorted-pins DUT board designs-Managed licenses, re-imaged and installed OS and software for the following ATE systems: Advantest T2000 Gen1/Gen2, Agilent Verigy 93K, & Teradyne Flex/J750-Created virtual and offline tester simulator farms for pattern conversion and program development for the above mentioned testers.

  • Test Engineering Manager, CPLD

    • 2000 - 2002

    -Managed four engineers/technicians during integration period after the acquisition of Philips CPLD group-Managed $250K overhaul of hand-wired TOPAZ engineering boards to more reliable custom PC boards-Created custom test pattern to replace (expired) Philips-licensed JTAG TAP controller verification pattern

  • Staff Test Engineer, CPLD

    • 1996 - 2000

    -Created unified wafersort and Final Test and QA programs for every device in the following CPLD families: XV9500, XL9500, & XC9500-Created vector engine to generate all patterns for the above mentioned families in the following formats: Verilog, TOPAZ, & Credence Logic100/Duo-Provided engineering lab and test floor IT support for the following testers: Credence Logic100 & TOPAZ-Invented, submitted, & received 2 separate U.S. Patents: 6363019 (Method and Circuit for Verifying Configuration of Programmable Logic Device) & 6630838 (Method for Implementing Dynamic Burn-in Testing Using Static Test Signals)

  • Senior Test/Product Engineer, CPLD

    • 1993 - 1996

    -Created test pattern generation system to replace hundreds of individual scripts and generate all patterns in Verilog, TOPAZ, Sentry 21, and LT1000/LT1101 formats-Overhauled wafersort, final test, QA, and characterization test programs to modularize the flow, reduce test time, and improve maintainability-Added TDR run-time de-skewing capabilities to the final test programs to increase tester signal accuracy and testability of high speed devices-Developed automated Vcc vs AC/DC parameter characterization capabilities-Developed test engineering capabilities to perform a full functional simulation of the new device on Verilog prior to first silicon-Added network capabilities to the TOPAZ PC-based test engineering system

• 

  Logic Devices

  • Product/Test Engineer, SRAM

    • 1989 - 1993

    -Developed production test, characterization, and wafersort capabilities for all SRAM devices-Developed 28 specialized characterization tools to support engineering functions on over 34 SRAM and logic devices-Developed bitmapping and redundancy repair capabilities for SRAMs-Developed user interface to automate collection of operator information, test yields, and characterization data from production runs for process control efforts-Performed evaluation and characterization of new 1 Megabit and 64K SRAMs-Maintained Sun-based Teradyne test systems and surrounding network

• 

  VLSI Technology Inc

  • Product Engineer, SRAM

    • 1987 - 1989

    -Developed methodology for introducing Statistical Process Control procedures to the test floor-Characterized and evaluated new SRAM products-Developed test procedures and debugged test programs for SRAM products-Converted manual data processing tasks to computer-assisted methods using PC, Macintosh, and VAX systems