Bio
Experience
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Principal Design Engineer
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Principal Design Engineer
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Jan 2007 - Present
(9 years 4 months)Lead Design Engineer on Fibre Channel and Ethernet Switching ASIC's.Architecture Design/Verilog coding and Verification of switching ASIC.Define IP architecture for ASIC Vendors that provide IP for Brocade ASIC's.Interface with software team on hardware architecture defi...
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Design Manager
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Jan 1999 - Jan 2007
Joined Nishan systems as a networking ASIC design Engineer. Nishan was a startup that was acquired byMcData Corporation.Worked on design and verification of ASIC/FPGA's for Fibre Channel Switching Products.Led a team of 15 engineers in ASIC development.Designed several blocks including shared...
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ASIC Design Instructor
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Jan 2000 - Jan 2002
Designed and taught courses in Verilog HDL, Design Simulation and Advanced Verilog at UCSC extensionas part of the ASIC Design Engineering course offering.
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Member of Technical Staff
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Jan 1993 - Jan 1999
(6 years 1 month)Page2Joined Nexgen Microsystems as an ASIC Design Engineer. Nexgen was acquired by Advanced MicroDevices.Worked on Nexgen 586/686 processor designs. Designed System Bus Interface blocks. Worked on physicaldesign and verification of several other blocks including cache controller ...
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Design Engineer
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Jul 1988 - Jan 1993
4 years 7 months)Design Engineer working on FPGA design for mini computers. Designed Bus Interface Controller andMemory Controller cards.
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Education
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Delhi College of Engineering
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San Jose State University
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Industry Focus. “Computer Networking”
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