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Crisalyn Chan

Staff Io Layout Design Engineer at On Semiconductor Corporation
Intro Book
Seasoned IC layout engineer with expertise in analog circuit design and layout.
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Location
Pocatello, Idaho, United States, US
Languages
  • English -
  • Tagalog -
  • Basic Japanese -
Skills
  • Design
  • Ic Layout Design
  • Pcb Design
  • Ic Es Evaluation
  • Manufacturing
  • Show all
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Bio

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Crisalyn Chan is a seasoned IC layout engineer with 21 years of experience in designing circuits for multipurpose ICs and leading block and chip layout design and physical verification. She has a strong background in analog layout requirements and expertise in EDA tools like Cadence Virtuoso XL/Layout Editor and Calibre.

Experience

  • On Semiconductor Corporation
    • Staff Io Layout Design Engineer

  • onsemi
    • United States
    • Semiconductors
    • 700 & Above Employee
    • Staff IP Layout Design Engineer
      • Oct 2022 - Present

    • Staff IC layout engineer
      • Feb 2012 - Oct 2022

      Worked with different onsemi design sites to lead and do block, and chip layout design and physical verification. Specialties:EDA Tools: Cadence Virtuoso XL/Layout Editor, VCAR, Mentor Graphics Pyxis, PCR (Pyxis Custom Router), Magwel, PowerVoltVerification Tools: Calibre Operating System: Unix (Solaris), Linux (Red Hat) -Has in-depth understanding of analog layout requirements (ESD, latch-up, electromigration, antenna effect, shielding, matching) -Knows how to estimates block size area, and chip size.

    • Circuit Design Engineer
      • Sep 2002 - Feb 2012

      Designing circuits for multipurpose ICs like motor driver ICs, LED drivers, Linear regulators, LDOs, operational amplifiers, and many more.

Education

  • 1995 - 2000
    Saint Louis University (PH)
    BS in Electronics and Communications Enginnering

Suggested Services

This profile is unclaimed. These are suggested service rates with 0% commision upon successful connection

Industry Focus. “Semiconductors.”

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