Experience

Logosent Semiconductors

• India
• Semiconductor Manufacturing
• 1 - 100 Employee

• Chief Executive Officer

  • Feb 2017 - Present

• Founder

  • Feb 2015 - Present

  www.logosent.com• Our Products: o Low-Cost FPGA development boards with RTL and software code generation support.o SParrow Rapid Prototyping Tool and Hardware Prototyping platforms that dramatically reduce the TTM of Digital Signal Processing systems. o SParrow enables the end-users to convert high-level DSP system concepts to fully integrated Hardware and Software systems that include DSP algorithms, software drivers and framework leveraging optimized libraries and code generation flows.o Our tools also provide a powerful and easy-to-use system modelling environment based on MATLAB for proof of concept as well as system integrity/accuracy cross checks.• Our Services: o Digital Signal Processing IP design and verification.o High-Speed ADC and AP-SOC/FPGA based system design and prototyping services.www.logosent.com



Texas Instruments

• United States
• Semiconductor Manufacturing
• 700 & Above Employee

• General Manager Processor BU System IP Design team

  • Jan 2013 - Jan 2015

  Led the team responsible for developing system power management and bus interconnect solutions for SOCs developed in WW Processors Business organization. These system IPs are architected and implemented to meet the system performance and low-power requirements of a wide range of devices that are developed for low-power medium performance Catalog/Industrial markets and high-performance med-low power ADAS/perf-Audio/DRI markets.

• General Manager Single Core ARM SOC (Sitara) Design team

  • Sep 2009 - Dec 2012

  Built and managed an SOC design team responsible for developing SOCs (SPEC to Tape-out/Qual) for the newly formed ARM MPU Business organization. Led end-to-end SOC design efforts for the pioneering Sitara (AM3x, AM4x) series devices. The team was also responsible for delivering various FPGA prototyping solutions for key IPs, implementation of the system/MPU-SubSystem IPs for the respective devices and development/deployment of EDA solutions for SOC integration/power estimation.

• SOC Design lead

  • Jan 2007 - Aug 2009

  Responsible for RTL to Tape-out or SOCs done under the DSPS India organization, leading the full SOC design team comprising of RTL, DV, DFTM, PD and Packaging sub-teams. Handled the role of RTL integration lead during the early part of this duration in 2007, before taking up the SOC design lead role in 2008.

• SOC Design lead and Front-end design manager

  • Jun 2003 - Dec 2006

  Responsible for RTL-to-Tape-out of SOCs done under the DSPS Houston organization. Led the complete front-end integration of TI's first DaVinci series device, followed by the full SOC design lead responsibility of two more DaVinci series devices. Additionally handled the Front-end design (SOC RTL, synthesis and DFT) team manager role for the Houston design team.

• CPU and Custom ALU Data-path Designer

  • Jan 2000 - May 2003

  Fully owned the design and implementation of the C64x M-Unit that handles 64 instructions of the C64x Instruction Set Architecture (ISA), including complex operations like DOTPs, Galois MPYs and MAC instructions. The design was optimized to meet the best in Industry DSP performance at that time (750MHz design target @ 1.2V for C027.A process). Additionally fully owned the first design and implementation of Software Pipe-lined Loop architecture in TI DSPs for C6x CPU along with required custom loop-buffers and instruction fetch/decode implementations.

• C62x DMA Design/Verification owner

  • Apr 1998 - Dec 1999

  Main responsibilities:- DMA module co-designer for C6202 and C6203 chips.- Developed a custom test-bench and a random test-pattern based verification suite to achieve high test-coverage of the relatively complex DMA module.



NCR Corporation

• United States
• IT Services and IT Consulting
• 700 & Above Employee

• Memory Controller ASIC Designer

  • Jan 1996 - Mar 1998

  Main responsibilities:- Designed a High Speed Memory Interface ASIC (0.35 micron technology, 100MHz clock, dual-interleaved zero-wait-state memory access) for an 8-way multiprocessing Intel P6 processor based system. - Worked on simulation and debug of the cache-coherency and the arbitration functionalities of a chip-set developed for an 8-way multiprocessing Intel P6 processor based system. Main responsibilities:- Designed a High Speed Memory Interface ASIC (0.35 micron technology, 100MHz clock, dual-interleaved zero-wait-state memory access) for an 8-way multiprocessing Intel P6 processor based system. - Worked on simulation and debug of the cache-coherency and the arbitration functionalities of a chip-set developed for an 8-way multiprocessing Intel P6 processor based system.



Wipro Infotech

• India
• IT Services and IT Consulting
• 1 - 100 Employee

• Hardware System and FPGA designer

  • Aug 1994 - Dec 1995

  Main responsibilities:- Design and development of an Intel 486DX processor based communication server with LAN Terminal Server (LTS) and Remote Access Server (RAS) functionalities. - Design and development of an Intel 960 SA RISK processor based Level-3 RAID (Redundant Array of Inexpensive Disks) controller PCI card.- Working as part of a 4-member team, the responsibilities included ORCAD based board design, FPGA/PLD implementation, component research/selection, board debug, and monitoring the FCC/CE certification process of the product.