Zihao Gong

Sr. Staff RF System Engineer at Tarana Wireless, Inc.
  • Claim this Profile
Contact Information
us****@****om
(386) 825-5501
Location
San Francisco Bay Area
Languages
  • English Professional working proficiency
  • Chinese Native or bilingual proficiency

Topline Score

Topline score feature will be out soon.

Bio

Generated by
Topline AI

5.0

/5.0
/ Based on 2 ratings
  • (2)
  • (0)
  • (0)
  • (0)
  • (0)

Filter reviews by:

David Hoffman

Zihao worked in my group at Cypress and I had the opportunity to work closely with him on several projects over an extended period. I also directly managed him for a time. Zihao is a bright young engineer who is constantly hungry to learn more. I saw him grow from an NCG fresh out of college into a very capable engineer able to lead projects and solve a wide variety of problems. One of the things I find striking about Zihao is that the rate of his learning and growth has been accelerating the entire time I've known him. This is a rare trait and bodes extremely well for his future. It's been a pleasure working with you Zihao!

Brett Shook

Zihao was my research partner while working on a software tool used to automate the design of power electronics modules. He worked diligently and thoughtfully to help bring about the first prototype of this software with me. Zihao is always willing to work his hardest and help others to achieve their goals. I would welcome Zihao to work with me any day.

You need to have a working account to view this content.
You need to have a working account to view this content.

Experience

    • United States
    • Telecommunications
    • 200 - 300 Employee
    • Sr. Staff RF System Engineer
      • Jul 2021 - Present

      Develop RF tests and improve system performance for wireless broadband access product. Develop RF tests and improve system performance for wireless broadband access product.

    • Semiconductor Manufacturing
    • 700 & Above Employee
    • Sr Staff RF DVT Engineer
      • Feb 2019 - Jun 2021

      WLAN Radio transceiver validation for Wifi 5/6/6E.● RF tests include power, phase noise, IM, EVM, gain, Rx-PER, NF, IP3, OOB spur/noise. ● Work along w/ radio designers to optimize RF performance. ● Familiar with WLAN PHY system features and calibrations. ● Impedance matching on board for minimum loss, optimal NF, and most power efficiency. ● In-house PA burn-in, deliver HTOL pattern, support ATE tests. ● Bench automation w/ Python, data parser/analysis, tcl, and shell scripting. Show less

    • Staff Product Engineer
      • Oct 2016 - Jan 2019

      WLAN/BT combo SoC NPI characterization and qualification ● Characterization over PVT on Teradyne uFlex, data analysis and review, set limits for final test program.● Performed reliability tests including ESD, LU, HTOL, and debugged failures ● Worked closely with ATE, design, marketing, QA, and packaging, as well as externally with subcon and vendors.

    • Sr Product Engineer
      • Sep 2012 - Sep 2016

      Sync-SRAM bench and ATE characterization ● Bench characterization for IPs in SRAM including Power-on-reset, IO, PLL, and Memory BIST. ● Hands on experience on ATE testers including Verigy 93k and Adv5593 for memory SoC .● Performed correlation analysis bench/ATE & wafer/package to improve yield, save cost, and ensure product quality. ● Experience with power delivery network analysis to improve high speed memory performance. ● Bench automation tests with NI instruments, Labview, and Teststand.● Familiar with other memories including nvSRAM, FRAM, and NOR/NAND flash. Show less

    • United States
    • Higher Education
    • 700 & Above Employee
    • Graduate Research Assistant
      • Aug 2010 - Jul 2012

      GRAPES (GRid-connected Advanced Power Electronic Systems) research center. Worked on a layout synthesis tool for multi-chip power electronic modules(MCPMs) to find the optimal layout design with best trade-off performance between thermal and electrical parasitics GRAPES (GRid-connected Advanced Power Electronic Systems) research center. Worked on a layout synthesis tool for multi-chip power electronic modules(MCPMs) to find the optimal layout design with best trade-off performance between thermal and electrical parasitics

Education

  • University of Arkansas at Fayetteville
    Master of Science (MS), Electrical and Electronics Engineering
    2010 - 2012
  • University of Arkansas at Fayetteville
    Bachelor's degree, Electrical and Electronics Engineering
    2007 - 2010

Community

You need to have a working account to view this content. Click here to join now