Experience

LeanMed, LLC

• United States
• Medical Device
• 1 - 100 Employee

• Electrical & System Engineering Lead

  • Mar 2021 - Present

  Lead the electrical engineering and embedded development of the smart telemetry monitoring system for the O2 Cube, our solar powered oxygen production solution targeted at rural health centers in underdeveloped countries. Work with our trusted vendors and industry partners to commercialize our first prototype. The O2 Cube project won the 2021 Pitt Innovation Challenge (Pinch) award as well as health disparity bonus award. Also check out our Wefunder campaign. Lead the electrical engineering and embedded development of the smart telemetry monitoring system for the O2 Cube, our solar powered oxygen production solution targeted at rural health centers in underdeveloped countries. Work with our trusted vendors and industry partners to commercialize our first prototype. The O2 Cube project won the 2021 Pitt Innovation Challenge (Pinch) award as well as health disparity bonus award. Also check out our Wefunder campaign.



Carnegie Mellon University

• United States
• Higher Education
• 700 & Above Employee

• Graduate Research And Teaching Assistant

  • Jan 2020 - Present

  • Research Ferromagnetic resonance (FMR) measurement with lab-on-chip interferometer using 10~16GHz VCO + RF frontend time-resolved fluorescence spectroscopy of biomarkers using novel on-chip barrel shifting 2D streak camera Minimally invasive epilepsy treatment using multi-polar RF lesioning • Head TA: 18721 – Advanced Analog Integrated Circuits Design (Spring 2022 - 2023) 18220 – Electronic Devices and Analog Circuits (Fall 2020) • Research Ferromagnetic resonance (FMR) measurement with lab-on-chip interferometer using 10~16GHz VCO + RF frontend time-resolved fluorescence spectroscopy of biomarkers using novel on-chip barrel shifting 2D streak camera Minimally invasive epilepsy treatment using multi-polar RF lesioning • Head TA: 18721 – Advanced Analog Integrated Circuits Design (Spring 2022 - 2023) 18220 – Electronic Devices and Analog Circuits (Fall 2020)



Cirrus Logic

• United States
• Semiconductor Manufacturing
• 700 & Above Employee

• Analog IP Design Intern

  • May 2022 - Dec 2022

  Developed the following IP blocks: fast startup bandgap reference (BGR), multi-level power on reset (POR), high voltage protection circuit, level shifters, and comparators. Developed the following IP blocks: fast startup bandgap reference (BGR), multi-level power on reset (POR), high voltage protection circuit, level shifters, and comparators.



Fermilab

• United States
• Research Services
• 700 & Above Employee

• Analog IC Design Intern

  • Jun 2020 - Nov 2020

  Designed and taped out a 12-bit 200MS/s low-noise charge integrating data-to-analog converter (QDAC) in 22nm FDSOI process. Tasks include design and layout of the circuit in Virtuoso and performing DRC/LVS/DFM/multi-patterning/parasitic extraction/fill-gen in Calibre. The DAC will act as the cryogenic ion trap controller, a key component within the next-gen quantum processor. Designed and taped out a 12-bit 200MS/s low-noise charge integrating data-to-analog converter (QDAC) in 22nm FDSOI process. Tasks include design and layout of the circuit in Virtuoso and performing DRC/LVS/DFM/multi-patterning/parasitic extraction/fill-gen in Calibre. The DAC will act as the cryogenic ion trap controller, a key component within the next-gen quantum processor.



Micron Technology

• United States
• Semiconductor Manufacturing
• 700 & Above Employee

• DRAM ATE Test Engineer III

  • Jun 2019 - Dec 2019

  • Promoted to drive DDR5 testing bringup and successfully led the qualification of Micron’s first 16GB 4800MT/s DDR5 product • Wrote DDR5 critical feature tests in ATPG and Python in accordance with JEDEC, tests including CA/CS pin training, read/write training, preamble training, decision feedback equalizer test, internal VrefCA/DQ/CS monitors • Coordinated DDR5 backend manufacturing logistics for test equipment, program readiness, and personnel training

• DRAM ATE Test Engineer I, II

  • Jul 2015 - Jun 2019

  Specialized in ATE testing of DRAM high speed circuitry through designing/running tests under stressed conditions, and collecting experiment statistics. Worked with product engineers to make sure our products meet rigorous timing/speed specifications. • Developed high speed reliability and quality test solutions in Python, ATPG, and Shmoo for enterprise DRAM by creating comprehensive test coverage, performing failure analysis, and lowering test times on Advantest/TechWing platform •… Show more Specialized in ATE testing of DRAM high speed circuitry through designing/running tests under stressed conditions, and collecting experiment statistics. Worked with product engineers to make sure our products meet rigorous timing/speed specifications. • Developed high speed reliability and quality test solutions in Python, ATPG, and Shmoo for enterprise DRAM by creating comprehensive test coverage, performing failure analysis, and lowering test times on Advantest/TechWing platform • Managed DRAM products throughout their lifecycle covering first silicon, internal qualification, and high-volume ramp-up • Assisted design/validation of proprietary high speed probe system with SI, CDR, and statistical analysis • Collaborated with Product Engineering on various DFT designs to enable online chip repair and improve chip yield • Wrote numerous automation scripts in Python and Bash for high volume manufacturing to enhance process efficiency



Western Digital

• United States
• Computer Hardware Manufacturing
• 700 & Above Employee

• Read/Write Channel Integration Intern

  • May 2013 - Dec 2013

  • Specialized in read/write channel analysis in enterprise hard drives (HDDs) • Collected statistics for high instability HDDs with inconsistent read head under different stresses • Used TCL to implement a virtual oscilloscope on PC to quickly display read head data • Specialized in read/write channel analysis in enterprise hard drives (HDDs) • Collected statistics for high instability HDDs with inconsistent read head under different stresses • Used TCL to implement a virtual oscilloscope on PC to quickly display read head data



Berenato Environmental Associates

• Ocean City, NJ

• CAD Intern

  • May 2012 - Aug 2012

  • Designed blueprints for oil pollution excavation/remediation using CAD software • Wrote mold removal license applications in all 50 states in U.S. • Designed blueprints for oil pollution excavation/remediation using CAD software • Wrote mold removal license applications in all 50 states in U.S.