Yung-Shao Shen

Senior Process Engineer at 台灣積體電路製造股份有限公司
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Contact Information
us****@****om
(386) 825-5501
Location
TW
Languages
  • English Full professional proficiency
  • Chinese Native or bilingual proficiency

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Bio

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Credentials

  • Certificate of General Engilsh Proficieny Test (GEPT) High-Intermediate level
    LTTC, The Language Training and Testing Center
    Jan, 2014
    - Nov, 2024

Experience

  • TSMC
    • Taiwan
    • Semiconductor Manufacturing
    • 700 & Above Employee
    • Senior Process Engineer
      • Jul 2021 - Present

      •N06/N07/N07+ FEOL PVD Thin-Film Deposition on ALD HK/Metal Gate Manufacturing.

    • Process Engineer
      • Oct 2016 - Sep 2021

      •N06/N07/N07+/N10 FEOL PVD Thin-Film Deposition on ALD HK/Metal Gate Manufacturing.•2019 Top On-Duty Engineer of PVD•Major Achievement: 1. Improve Yield~0.5% by defect trouble shooting DOE & KLA Wafer defect inspection system.2. Reduce Vt/Igi/VBD RtR sigma~30% by tightly control & CIP for key process impact factors.3. Enlarge tool capicity~13% by wafer transfer logic optimize & process bottleneck improvement.4. Minimize waste on tool/chemical~25% by tool parts life time prolong, CIP parts & 2nd source chemical evaluation.•Skills: 1. AMAT/ASM Semiconductor Manufacturing Operation2. KLA Wafer Defect Analysis3. KLA-Tencor Thin Film Spectra/Rs Measurement4. REVERA XPS Measurement5. WAT/CP Test & Data Analysis

Education

  • 國立清華大學
    Master of Engineering - MEng, Department of Engineering and System Science
    2014 - 2016

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