Experience

ZYLtech Engineering LLC

• United States
• Appliances, Electrical, and Electronics Manufacturing
• 1 - 100 Employee

• Lead Software Engineer

  • Jun 2020 - Present



Wayne State University

• United States
• Higher Education
• 700 & Above Employee

• Postgraduate Researcher

  • Aug 2016 - Jun 2020

  – Provided an interactive sound interface for RoS to copy photos to designated folders–Created Alexa skills to identify photo copying commands.– Developed in Node.js/JS/HtmlCredit-Fairness Research– Proposed a novel credit fairness by taking into account task durations– Assured the properties of fairness.– Improved job completion times by 21% and reduced makespan by 9% while assuring creditfairness– Developed in Linux, Java

• Research Assistant

  • Sep 2010 - Aug 2016

  Credit-Sharing-oriented Network and Locality-aware Scheduling in Clusters– Proposed a novel credit sharing policy theoretically guaranteeing that not a single job will have a longer completion time than that under the dominant resource fairness policy with the same workload in online scheduling. It not only accelerates jobs but also unleashes the power of packing. – Locality and Network-aware scheduling is incorporated into the policy seamlessly for improving disk and network utilization.– Presented Dynamic-Level to optimize both completion times and system efficiency, resulting in speedup of jobs by up to 2.36 time, reduction of makespan by 27%. Moreover, not a single job’s execution time under CANAL becomes longer than that under DRF.– Developed in Linux, JavaAutomatic Cloud Resource Management– Proposed a novel integrated optimal and feedback control approach for balanced configuration of multi-resources for response time guarantee in virtualized clusters. The approach leads to at least 30% less resource allocations, and 35.6% more stable QoS provisioning compared to a competitive approach without feedback– Tuned VCPU capping to dynamically guarantee response time by using a new control method, resulting in 7% better stability, and better responsiveness– Developed in Linux, C Show less



Agate Logic

• United States
• Semiconductor Manufacturing
• 1 - 100 Employee

• Software Engineer

  • Feb 2008 - Aug 2010

  R & D on Verilog Synthesis Tool – Verified QoS (timing & area) and logical correctness of functionality by defining test plan, writing scripts, and designing test cases for each feature, and interacted with vendor to cleanup issues – Added many features, such as error reporting, latch inferring, blocking statement synthesis etc, and verified synthesis results using Formality tool. Optimized synthesis results by constant propagation, constant folding and copy propagation methods, leading to 30% better QoS – Developed in Windows, Linux, C++, Bison Show less