Experience

Altera

• United States
• Semiconductors
• 700 & Above Employee

• Senior Member of Technical Staff

  • Jul 1998 - Present

  • Responsible for selections of BOM and constructions such as substrate BU and core , SM, wonderful, TIM, bump pitch and size, UBM size and SMO size for every generation products including N40, N28, N20 and N14 • Actively involved in the development of large-die full-array Cu bump FCBGA, WLCSP, FOWLP, FCCSP, FCmBGA, F2F, 2.1D, core-less substrate, 2.5D • Responsible for providing extremely low cost package solutions for FPGAs for IoT iniative. Developed a cost matrix of various small… Show more • Responsible for selections of BOM and constructions such as substrate BU and core , SM, wonderful, TIM, bump pitch and size, UBM size and SMO size for every generation products including N40, N28, N20 and N14 • Actively involved in the development of large-die full-array Cu bump FCBGA, WLCSP, FOWLP, FCCSP, FCmBGA, F2F, 2.1D, core-less substrate, 2.5D • Responsible for providing extremely low cost package solutions for FPGAs for IoT iniative. Developed a cost matrix of various small form factor packages • Started and leading the qualification of a very low-cost WLCSP with a new OSAT • Lead a team to evaluate next generation materials for high performance products, focusing on substrate BU and core and 130-150um pitch first • Responsible for developing modeling methodology in delivering thermal resistances and compact thermal models for MCP (multi-chip package) • Developed FEM models to study CPI stress for MCP with Si bridges embedded in substrate • Developed CFD thermal models for MCP to analyze the device thermal performance under various powers and system conditions • Responsible for developing and updating roadmaps for packaging materials and thermal management • Led the development of low theta-JC FCBGA, improving theta-JC from 0.5 to 0.3 °C. cm2/W • Developed several reference cooling solutions for 100 - 150W FCBGA devices • Developed thermal and mechanical models for 2.5D. Studied effect on reliability of package constructions such as thickness of interposer and dies, and die layout. Compared the pros and cons of various process flows. Analyzed the impact of underfills, TIM and adhesives and proposed an optimized BOM • Responsible for generating package thermal resistances and compact thermal models for every device. Responsible for providing customers thermal support and solutions in diverse applications • Built up accurate modeling capabilities to predict solder joint reliability, component-level reliability and warpage Show less • Responsible for selections of BOM and constructions such as substrate BU and core , SM, wonderful, TIM, bump pitch and size, UBM size and SMO size for every generation products including N40, N28, N20 and N14 • Actively involved in the development of large-die full-array Cu bump FCBGA, WLCSP, FOWLP, FCCSP, FCmBGA, F2F, 2.1D, core-less substrate, 2.5D • Responsible for providing extremely low cost package solutions for FPGAs for IoT iniative. Developed a cost matrix of various small… Show more • Responsible for selections of BOM and constructions such as substrate BU and core , SM, wonderful, TIM, bump pitch and size, UBM size and SMO size for every generation products including N40, N28, N20 and N14 • Actively involved in the development of large-die full-array Cu bump FCBGA, WLCSP, FOWLP, FCCSP, FCmBGA, F2F, 2.1D, core-less substrate, 2.5D • Responsible for providing extremely low cost package solutions for FPGAs for IoT iniative. Developed a cost matrix of various small form factor packages • Started and leading the qualification of a very low-cost WLCSP with a new OSAT • Lead a team to evaluate next generation materials for high performance products, focusing on substrate BU and core and 130-150um pitch first • Responsible for developing modeling methodology in delivering thermal resistances and compact thermal models for MCP (multi-chip package) • Developed FEM models to study CPI stress for MCP with Si bridges embedded in substrate • Developed CFD thermal models for MCP to analyze the device thermal performance under various powers and system conditions • Responsible for developing and updating roadmaps for packaging materials and thermal management • Led the development of low theta-JC FCBGA, improving theta-JC from 0.5 to 0.3 °C. cm2/W • Developed several reference cooling solutions for 100 - 150W FCBGA devices • Developed thermal and mechanical models for 2.5D. Studied effect on reliability of package constructions such as thickness of interposer and dies, and die layout. Compared the pros and cons of various process flows. Analyzed the impact of underfills, TIM and adhesives and proposed an optimized BOM • Responsible for generating package thermal resistances and compact thermal models for every device. Responsible for providing customers thermal support and solutions in diverse applications • Built up accurate modeling capabilities to predict solder joint reliability, component-level reliability and warpage Show less



University of Colorado Boulder

• United States
• Higher Education
• 700 & Above Employee

• Research Associate

  • Oct 1997 - Jul 1998

  Center for Advanced Manufacturing and Packaging of Microwave, Optical and Digital Electronics (CAMPmode) Conducted research on BGA, CSP and flip chip Provided consultations on SMT process development Center for Advanced Manufacturing and Packaging of Microwave, Optical and Digital Electronics (CAMPmode) Conducted research on BGA, CSP and flip chip Provided consultations on SMT process development



Exabyte Corp

• SMT Engineer

  • Mar 1996 - Oct 1997

  • Implemented organic solderability preservative (OSP) and no-clean surface mount process • Eliminated wave and manual soldering by applying intrusive reflow and press-fit processes • Implemented organic solderability preservative (OSP) and no-clean surface mount process • Eliminated wave and manual soldering by applying intrusive reflow and press-fit processes