Yu-Hsuan Cheng

Project Manager at eMemory
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Contact Information
us****@****om
(386) 825-5501
Location
TW
Languages
  • 中文 -
  • 英文 -

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Bio

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Experience

  • eMemory
    • Semiconductor Manufacturing
    • 1 - 100 Employee
    • Project Manager
      • May 2021 - Present

      1. Rram Design 2. Flash Design 1. Rram Design 2. Flash Design

  • Elite Semiconductor Microelectronics Technology Inc
    • Taiwan
    • Semiconductor Manufacturing
    • 1 - 100 Employee
    • Senior Staff Engineer
      • Apr 2012 - May 2021

      1. Designed internal & external power — First 4Gb density DRAM in ESMT — Added voltage tuning function for testing easier 2. Enhanced e-fuse function — Added parallel to series function for reducing signal lines 3. Developed ZQ calibration, OCD and SSN — First ZQ calibration function in ESMT — Added new function for multi chip package 4. Verified DRC, LVS, ESD and ERC 5. Compiled command file of LVS, ESD and ERC 6. Established testbench of function and testmode 7. Developed input buffer and modified setup and hold time 8. Built IBIS file

Education

  • National Chung Cheng University
    MS, Electrical and Electronics Engineering
    2009 - 2012
  • National Dong Hwa University
    bachelor, Electrical Engineering
    2005 - 2009

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