Experience

Veriest

• Israel
• Semiconductor Manufacturing
• 100 - 200 Employee

• Design Verification Engineer

  • Jan 2017 - Present

  Design Verification & Emulation Engineer at Veriest Solutions Design Verification & Emulation Engineer at Veriest Solutions



Intel Corporation

• United States
• Semiconductor Manufacturing
• 700 & Above Employee

• VLSI Engineer

  • 2013 - Jan 2017

  VLSI Logic Designer: • Design of 200G Eth. PHY PCS layer RX. • Design of a management module for Ethernet PHY (Host I/F with DMA, AMBA AHB-Lite interconnect matrix, clock, reset, initialization, etc.). VLSI Logic Verificator: • Functional verification of Ethernet PHY (constrained-random scenarios, assertion-based checkers, coverage, etc.) on an OVM based SystemVerilog platform. VLSI Logic Designer: • Design of 200G Eth. PHY PCS layer RX. • Design of a management module for Ethernet PHY (Host I/F with DMA, AMBA AHB-Lite interconnect matrix, clock, reset, initialization, etc.). VLSI Logic Verificator: • Functional verification of Ethernet PHY (constrained-random scenarios, assertion-based checkers, coverage, etc.) on an OVM based SystemVerilog platform.



NXP acquires Freescale Semiconductor

• United States
• Semiconductor Manufacturing
• 700 & Above Employee

• VLSI Engineer

  • 1998 - 2013

  Validation tool specialist: • Develop a tool and test-bench for running all emulation (pre-silicon) and validation (post-silicon) tests of large SoC products. Build a unified work environment for all SoC needs: Fast-Simulation, Emulation, Validation, Field testing and Debug of customer issues. Fully portable (Linux/Windows OS). Including compile and link of the test software, DUT connection and control, test list management, etc. • Build Emulator model and test-bench for Palladium emulator (Synthesis & Compilation). VLSI Logic Verificator: • Functional verification in unit-level and SoC-level: Develop verification strategy based on coverage-driven, directed and constrained-random approach. Prepare test plans, build checkers and generate high-coverage scenarios. • Work with both SystemVerilog and C++ platforms. • Specialized in Data-Link and Network layers of High Speed Serial Interfaces (PCIe, SerialRapidIO). • Also covered Power-up sequence, out-of-reset configuration and SoC Internal Boot program (embedded ROM S/W). VLSI Logic Designer: • Design of VLSI devices: micro-architecture definition, RTL coding, and synthesis. • Specialized in clocking and reset of large SoC. Expert in development of clocking/reset methodology. Designer of modular clock controllers with re-configurable clock scheme and on-the-fly frequency variation. • Design of memory interface in a multi-die device. VLSI Custom-Memory Designer: • Design & Modeling of custom memory arrays, clock/reset tree, special signals and power-distribution nets. Well acquainted with layout parasitic capacitance and resistance and their effect on signal integrity, power consumption and speed. Show less



Israel Defense Forces

• Communications Engineer

  • 1992 - 1998

  Technical Project Manager: • Specification, SOW and Project Management of military communication systems and communications infrastructure. Technical Project Manager: • Specification, SOW and Project Management of military communication systems and communications infrastructure.