Experience

Tabula

• United States
• Semiconductors
• 1 - 100 Employee

• Staff Software Engineer

  • Jun 2007 - Present

  I joined Tabula's Software Infrastructure team in 2007. My first task was to develop the configuration tool from scratch, and I was able to complete work on the basic functionality of the tool and get it up and running in only four weeks. Today this tool not only creates bit stream for Tabula's parts, but also contains features such as DRC, power optimization, and various other features designed to cope with hardware limitations. I also wrote Tabula's clock planning, routing and placement tool from scratch. This tool creates a complete clock network and is used in different stages of the software flow. During my tenure at Tabula, I wrote more than one hundred thousand lines of C++ code, which are used in all of the Tabula's products. I have had the opportunity to interact with many colleagues from various different departments, which was essential in accomplishing all of my tasks successfully. Show less



Magma Design Automation

• United States
• Semiconductors
• 1 - 100 Employee

• Member of Consulting Staff

  • Sep 2004 - May 2007

  I worked in Mojave LVS project from the early stage of the project. I designed and implemented many fundamental algorithms in Magma’s Quartz LVS tool, including device extraction, net list organization, hierarchical handling, compare labeling algorithm, and TCL interface design. Worked on designs from various customers for LVS debugging and supporting. I also coded run decks for various manufacturers for 130nm, 90nm, 65nm and 45nm processes. In some cases, I went to customer site to support our tools on real large designs. Show less



Ammocore Technology, Inc.

• Santa Clara

• Principle Engineer

  • 2003 - 2004

  After joining Ammocore's timing analysis team, I created and implemented a path search algorithm to calculate timing for a specific path. I designed and constructed a new timing constraint format suitable with Ammocore’s design methodology. I also supported and maintained the timing analysis tool on various designs and applications. After joining Ammocore's timing analysis team, I created and implemented a path search algorithm to calculate timing for a specific path. I designed and constructed a new timing constraint format suitable with Ammocore’s design methodology. I also supported and maintained the timing analysis tool on various designs and applications.



Cadence Design Systems

• San Jose, CA

• Member of Consulting Staff

  • 2002 - 2003

  I designed and implemented a redundant via insertion program to address the manufacturability issues in IC designs. I also created a methodology for metal fill and spacing in the physical layout, which required some fundamental geometry manipulation functions, including geometry Boolean operations and sizing operations. I designed and implemented a redundant via insertion program to address the manufacturability issues in IC designs. I also created a methodology for metal fill and spacing in the physical layout, which required some fundamental geometry manipulation functions, including geometry Boolean operations and sizing operations.



Numerical Technologies, Inc.

• San Jose, CA

• Staff Engineer

  • 2000 - 2002

  I joined the Phase Shifting Mask (PSM) group as a senior engineer. I was involved in various efforts in PSM design. I invented a DRC checking algorithm for PSM shifters and OPC biases. My responsibilities include development and support of flows and methodologies for mask rule checking, geometry manipulation functions, etc. I joined the Phase Shifting Mask (PSM) group as a senior engineer. I was involved in various efforts in PSM design. I invented a DRC checking algorithm for PSM shifters and OPC biases. My responsibilities include development and support of flows and methodologies for mask rule checking, geometry manipulation functions, etc.



SGI

• United States
• Computer Hardware
• 500 - 600 Employee

• Member of Technical Staff

  • 1996 - 2000

  I was responsible for continuous development of the in-house router. I successfully supported multiple MIPS chip design activities, including floor planning, initial and final timing analysis, top level routing and block internal routing. I designed and implemented top level distributed and parallel routing mechanism using LSF and C language. I also wrote significant amount of SKILL code for the graphic interface between the in-house router and Cadence Virtuoso. I was responsible for continuous development of the in-house router. I successfully supported multiple MIPS chip design activities, including floor planning, initial and final timing analysis, top level routing and block internal routing. I designed and implemented top level distributed and parallel routing mechanism using LSF and C language. I also wrote significant amount of SKILL code for the graphic interface between the in-house router and Cadence Virtuoso.



SGI

• United States
• Computer Hardware
• 500 - 600 Employee

• Summer Intern

  • May 1995 - Sep 1995

  During that summer, I created and implemented a floor plan/placement optimization algorithm, which used the global routing results to minimize the chip size during floor plan stage. During that summer, I created and implemented a floor plan/placement optimization algorithm, which used the global routing results to minimize the chip size during floor plan stage.