Wade Ho
Physical Design at Rivos Inc.- Claim this Profile
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Chinese Native or bilingual proficiency
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English Professional working proficiency
Topline Score
Bio
Experience
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Rivos Inc.
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United States
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Computer Hardware Manufacturing
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100 - 200 Employee
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Physical Design
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Dec 2022 - Present
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Ambiq
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United States
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Semiconductor Manufacturing
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100 - 200 Employee
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Staff Engineer, Physical Design
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Jan 2022 - Dec 2022
Physical Design for ultra low power circuits Physical Design for ultra low power circuits
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Synopsys Inc
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United States
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Software Development
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700 & Above Employee
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Senior Application Engineer
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Jun 2019 - Jan 2022
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MediaTek
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Taiwan
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Semiconductor Manufacturing
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700 & Above Employee
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Physical Design Senior Engineer
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Aug 2015 - Jun 2019
Experienced in advanced process (7nm, 12nm, 16nm, 28nm) APR implementation. Wei-Da Ho has complete seven physical design projects in Mediatek, including critical block, high instance count design, high-speed design, low-power design, block coordinator, and top hierarchical design. Experienced in advanced process (7nm, 12nm, 16nm, 28nm) APR implementation. Wei-Da Ho has complete seven physical design projects in Mediatek, including critical block, high instance count design, high-speed design, low-power design, block coordinator, and top hierarchical design.
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Faraday
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Taiwan
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Semiconductor Manufacturing
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300 - 400 Employee
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Physical Design Flow Senior Engineer
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Sep 2012 - Aug 2015
Wei-Da Ho worked in Faraday Technology Corporation (2012 ~ 2015). Wei-Da Ho in charge of physical design and its related flow, including place & route implementation, RC extraction, flow automation, and other EDA tools' research. Current job position: Adopts UMC's advanced process (55nm, 40nm, 28nm, etc..), and develops these processes in Faraday's back-end flow. Wei-Da Ho worked in Faraday Technology Corporation (2012 ~ 2015). Wei-Da Ho in charge of physical design and its related flow, including place & route implementation, RC extraction, flow automation, and other EDA tools' research. Current job position: Adopts UMC's advanced process (55nm, 40nm, 28nm, etc..), and develops these processes in Faraday's back-end flow.
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Education
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National Chung Cheng University
Master's degree, Computer Science