Václav Hummel

CPU Design Engineer at Tachyum
  • Claim this Profile
Online Presence
Contact Information
Location
SK
Languages
  • English Full professional proficiency
  • Czech Native or bilingual proficiency
  • German Limited working proficiency

Topline Score

Bio

Generated by
Topline AI

0

/5.0
/ Based on 0 ratings
  • (0)
  • (0)
  • (0)
  • (0)
  • (0)

Filter reviews by:

No reviews to display There are currently no reviews available.

0

/5.0
/ Based on 0 ratings
  • (0)
  • (0)
  • (0)
  • (0)
  • (0)

Filter reviews by:

No reviews to display There are currently no reviews available.
You need to have a working account to view this content. Click here to join now

Experience

    • United States
    • Computer Hardware Manufacturing
    • 1 - 100 Employee
    • CPU Design Engineer
      • Jun 2021 - Present
    • Austria
    • Software Development
    • 1 - 100 Employee
    • Digital Design Engineer
      • Sep 2018 - Jun 2021
    • IT Services and IT Consulting
    • 100 - 200 Employee
    • Digital design Engineer
      • Aug 2012 - Aug 2018

      I joined Liberouter project by CESNET in 2012 as digital desing developer just after 2 semesters at the university. My first task was to implement and verify by functional verification output network module at MAC sublayer for 100 Gb/s Ethernet. The output network module is part of the NetCOPE-100G framework running on COMBO-100G FPGA card. Later I created hardware accelerated network application packet capture&replay as my Bachelor's thesis. The next task was to implement few components for Software Defined Monitoring concept created by the Liberouter team. I created my own bitstreams for FPGA to test these components on real hardware COMBO-100G. Another task was to create automated tests for our network interface cards using Spirent TestCenter. These tests were implemented in TCL. I also performed debugging of FPGA designs on COMBO-100G cards. Then I started to work on my Master's thesis Framework for Hardware Acceleration of 400Gb Networks. In fact, it is the next generation of the NetCOPE-100G framework. Clean sheet design was created due to limitation of the current framework. Proposed solution scales well even beyond 400Gb. Critical parts were implemented and ephasis was put on high frequency (more than 400MHz). After graduation at the university I continue with implementation in order to deploy proposed framework on real hardware soon. Show less

Education

  • Brno University of Technology
    Master's degree, Embedded systems
    2014 - 2017
  • Technische Universität Graz
    Computer science
    2015 - 2016
  • Brno University of Technology
    Bachelor's degree, Information technology
    2011 - 2014

Community

You need to have a working account to view this content. Click here to join now