Vincent Leduby
A3 (ADAS,AV,AI) Business Line Director at LACROIX - Impulse- Claim this Profile
Click to upgrade to our gold package
for the full feature experience.
-
English Full professional proficiency
-
French Native or bilingual proficiency
-
Spanish Elementary proficiency
Topline Score
Bio
0
/5.0 / Based on 0 ratingsFilter reviews by:
Experience
-
LACROIX - Impulse
-
France
-
Telecommunications
-
1 - 100 Employee
-
A3 (ADAS,AV,AI) Business Line Director
-
May 2021 - Present
Scope of A3 Business Line is ADAS, Autonomous Vehicles and AI
-
-
Director - AI, ADAS, Autonomous Vehicles Business line (former eSoftThings)
-
Nov 2020 - Present
-
-
Co-Founder and Director - Autonomous Vehicles BU (former eSoftThings)
-
Feb 2014 - May 2021
-
-
-
-
Senior System Architect, Modem Platform Solution
-
Dec 2010 - Mar 2014
leading RMC Modem Platforms (2G/HSPA+/LTE FDD/TDD) technical definition and architecture for Mobile Broadband routers, Handheld (modem connected to 3rd party application processor), embedded modem, M2M modem market segments Core Activity: - Requirement Gathering based on customer feedback,standardization, Operators, competition analysis - Requirements (Feature & KPIs) and critical use cases definition - Top Level HW/SW Platform Architecture (clocks, supplies, resets, CPUs, memories, buses, interfaces and SW partitioning and interfaces) - Platform Modeling (Power, Performances) and KPIs estimations - Definition of SOW, work-split and interfaces for each strategic partnership - System design work coordination for modem platform development programs - 3rd party component selection process : Definition of technical criterias Technical domains coverage (DBB Subsystem, RF Subsystem, Audio Subsystem, Power management, Modem SW interfaces, InterProcessor communocation, CPU and clock speed dimensioning) Promotion of 2G/HSPA+/LTE RMC modem Platform to customers. Workshop coordination Show less
-
-
-
Renesas Design France
-
France
-
Civic and Social Organizations
-
SW Department Manager
-
2005 - Dec 2010
2G/3G/LTE L1/RF and Audio embedded SW Department Manager (20+ people)Leading SW activities (CPU ARM9, Cortex R4, Renesas H8S - DSP NXP Coolflux, Renesas D20V) --- Requirements and System Specification (HW/SW partitioning, CPU clock dimensioning) --- SW Design, implementation, optimization and integration on Emulation platform --- SW Maintenance - Validation and Customer support Activity coordination, planning and Quality processPeople line management
-
-
2G Technology Program Manager
-
Mar 2009 - Nov 2010
In charge of 2G features roadmapping for RENESAS 2G/HSPA+/LTE modem platform developed in collaboration with Fujitsu, for WorldWide market. .• 2G Features Promotion to DoCoMo operator for 2G/HSPA+/LTE products• Leading advanced studies and platform development activities of 2G Features includingplatform Requirements, L1 Algorithm development, HW/SW partitioning, L3/L2/L1 SW design, development and Validation• People cross-management, coordination, planning,quality process
-
-
DSP team Manager
-
Jan 2005 - Mar 2006
2G L1 and Audio DSP SW Department Manager (10+ people)• Leading DSP FW activities --- Requirements and 3GPP follow up--- 2G L1 FW/HW Algorithm design (Equalizer, Channel coding, Detection, ...) --- System Specification (HW/SW partitioning, IPC, DSP clock & memory footprint dimensioning)--- SW Design, implementation and integration on Emulation platform--- SW Maintenance - Validation and Customer support • Activity coordination, planning and Quality process• People line management Show less
-
-
-
-
2G/3G Physical Layer - DSP leader
-
2002 - 2004
Dual Mode Modem product - 2G/3G Physical layer Technical leader• System Specification (HW/FW partitioning, IPC, DSP clock & memory footprint dimensioning)• FW Design - FW module split and specification (Interfaces, Design specifiation, Unit test)• DSP software development and MIPS optimization (Analog Devices DSP Blackfin)
-
-
2G L1 - DSP Engineer
-
Jun 1998 - Apr 2002
DSP FW engineer for GSM/EGPRS mobile platform• System Specification (HW/FW partitioning, IPC, DSP clock & memory footprint dimensioning)• FW Design - FW module split and specification (Interfaces, Design specifiation, Unit test)• DSP software development and MIPS optimization(Partus CEVA 'Oak' and 'TeakLite' and 'PALM' DSP, TI TMS320C51 DSP)
-
-
-
Syseca
-
Software Development
-
1 - 100 Employee
-
SW engineer
-
1997 - 1998
-
-
Education
-
IFSIC - Institut de Formation Superieure en Informatique et Télécommunications
Master's degree in computing science, Signal Processing and Telecommunication