Experience

Condor Computing Corporation

• United States
• Semiconductor Manufacturing
• 1 - 100 Employee

• Senior Principal Design Verification Lead

  • May 2023 - Present

  RISC-V CPU Verification RISC-V CPU Verification


DVCon U.S.
• Semiconductor Manufacturing
• 1 - 100 Employee
• Technical Program Committee member, Session Chair

  • Aug 2019 - Present


Microsoft

• United States
• Software Development
• 200 - 300 Employee

• Principal Cache Sub-System Verification Engineer

  • Jan 2022 - May 2023

  Azure Cloud Silicon Design: Cache Subsystem Verification. Azure Cloud Silicon Design: Cache Subsystem Verification.



Samsung SARC | ACL

• Sr.Staff GPU Verification Engineer

  • Aug 2018 - Jan 2022

  Cache Coherency and UVM Expert. Quickly built Muti GPU Core UVM Bench for Memory Subsystem Cluster Verification that includes L1, L2 Caches, NOCs, MMU and DMA Controllers. Cache Coherency and UVM Expert. Quickly built Muti GPU Core UVM Bench for Memory Subsystem Cluster Verification that includes L1, L2 Caches, NOCs, MMU and DMA Controllers.



Centaur Technology

• United States
• Computer Hardware Manufacturing
• 1 - 100 Employee

• CPU Verification Engineer

  • Dec 2014 - Jul 2018

  X86 Processor Verification. Cache Coherency and UVM Expert. Developed single handedly an UVM block level testbench from scratch for a brand new L2 design. Develped single handedly a UVM Sub System level test bench with L2, L3 and Coherent Interconnect with one x86 Core + 7 Fake CPUs. Created complex UVM Test sequences that effectively helped to find a lot of bugs including corner case bugs in L2, L3 and Coherent Interconnect. X86 Processor Verification. Cache Coherency and UVM Expert. Developed single handedly an UVM block level testbench from scratch for a brand new L2 design. Develped single handedly a UVM Sub System level test bench with L2, L3 and Coherent Interconnect with one x86 Core + 7 Fake CPUs. Created complex UVM Test sequences that effectively helped to find a lot of bugs including corner case bugs in L2, L3 and Coherent Interconnect.

• Sr.Staff Engineer

  • Nov 2012 - Nov 2014

  CPU/GPU Front End/Verification Methodology. Coherent Interconnect Verification. Memory Controllers CPU/GPU Front End/Verification Methodology. Coherent Interconnect Verification. Memory Controllers



Marvell Semiconductor

• 1 - 100 Employee

• Sr.Staff Verification Engineer

  • Jun 2008 - Oct 2012

  Verification Lead for DDR3/4 Memory Controller IP using System Verilog, VMM, UVM and SVA. Created several Block level, and SOC level tesbenches from scratch in VMM and OVM. Regression enviroments, Scritps, Code/Assertions/Founctional coverage closure. Clock Domain Crossing, Performance Measurement/Regressions. IP Delivery / Support. Post SIlicon Debugging. Application Processors, Storage SOCs. Memory Controller - DDR2, DDR3, LPDDR2 and DDR4 for Storage, Wireless, Multimedia SOCs. Highly Configurable DMA, PCI Express, AXI Interconnects. Verification Methodologies, and Verification IPs. Show less



Mentor Graphics Corporation

• Staff Verificaton Engineer

  • Sep 2005 - Jun 2008

  Assertion IPs, Questa Verification Library, SV Based Verification IP Development. System Verilog, Assertions (SVA/PSL), Formal, AVM, OVM. Protocols: AXI, SATA, PCI Express, GigaBit Ethernet, and I2C Assertion IPs, Questa Verification Library, SV Based Verification IP Development. System Verilog, Assertions (SVA/PSL), Formal, AVM, OVM. Protocols: AXI, SATA, PCI Express, GigaBit Ethernet, and I2C



Synopsys Inc

• United States
• Software Development
• 700 & Above Employee

• Manager R&D

  • Dec 2002 - Aug 2005

  Managed a team and 3 external partners for the development of Assertion IPs for AMBA AHB, PCI, AMBA AXI, PCI Express, DDR2, OCP, USB 2.0 and SMIA.Worked with Marketing, and VCS engineering teams on schedule, packaging and productization of Assertion IPs with VCSWorked with customers on supporting, BETA deployment, collaborative development of Assertion IPs in Simulation and Formal (Magellan).

• Engineering Project Leader

  • Dec 2002 - Oct 2004

  Developed/Lead Assertion IP Development in OVA for standard protocols such as AGP 3.0, PCI X 2.0, and AMBA AHB.Setup Methodology and created Engineering document for Assertion IP development to be able to use with VCS and Formal tool Magellan.Trained Team members, Customers, Partners on OVA, SVA, Magellan, and Assertion IP development.Developed OVL-OVA (OVL standards in OVA) checcker library that is being shipped with VCS.Worked with customers on supporting, BETA deployment, collaborative development of Assertion IPs in Simulation and Formal (Magellan). Show less



Sasken Communication Technologies Ltd

• Senior Hardware Engineer

  • Apr 2000 - Dec 2002

  Worked on 10+ Protocol Monitor development. All Monitors were used by customers. Received many appreciations by 0-In for technical excellence while developing these monitors, and by various end-customers for the quick Enhancements/bug-fixes.. CheckerWare Library: Developed/Guided/Reviwed complex checkers that are part of CheckerWare library such as Assert Window, Arbiter, FIFO, Multi-clock FIFO, and Multi-clock/Multi-port Memory access checkers. Worked on 10+ Protocol Monitor development. All Monitors were used by customers. Received many appreciations by 0-In for technical excellence while developing these monitors, and by various end-customers for the quick Enhancements/bug-fixes.. CheckerWare Library: Developed/Guided/Reviwed complex checkers that are part of CheckerWare library such as Assert Window, Arbiter, FIFO, Multi-clock FIFO, and Multi-clock/Multi-port Memory access checkers.



VXL Instruments

• Software Development
• 1 - 100 Employee

• Hardware Engineer

  • Sep 1997 - Apr 2000

  Design and Development of Electronics products: Thin Clients, and LAN Terminals, Computer Analog Monitors developement, POS Terminals and Cash Registers, Analog/Power Electronics Design: Switched Mode Power Supply Design, DC/DC Converters, Single Chip PWM based power supplies, EMI/EMC, Safety considerations, Digital Design: 8085 Microprocessor designs, Microcontrollers, ISA Bus Based PC add-on cards, x86 Assembly Language, 'C' Programming, HDL programming for CPLD/FPGA, Design and Development of Electronics products: Thin Clients, and LAN Terminals, Computer Analog Monitors developement, POS Terminals and Cash Registers, Analog/Power Electronics Design: Switched Mode Power Supply Design, DC/DC Converters, Single Chip PWM based power supplies, EMI/EMC, Safety considerations, Digital Design: 8085 Microprocessor designs, Microcontrollers, ISA Bus Based PC add-on cards, x86 Assembly Language, 'C' Programming, HDL programming for CPLD/FPGA,