Experience

Accedian is now part of Cisco

• Canada
• IT Services and IT Consulting
• 200 - 300 Employee

• FPGA Designer

  • Jan 2016 - Present

  - Implemented designs in Altera Stratix V FPGAs and Xilinx 7 series FPGAs - Responsible for creating and maintaining a common implementation flow - FPGA design: . implemented arithmetic functionalities using Xilinx 7 series DSP48E1 primitives or Altera Stratix V DSP component. . modified and verified LPDDR2 and DDR3 Memory Controller designs - Implemented designs in Altera Stratix V FPGAs and Xilinx 7 series FPGAs - Responsible for creating and maintaining a common implementation flow - FPGA design: . implemented arithmetic functionalities using Xilinx 7 series DSP48E1 primitives or Altera Stratix V DSP component. . modified and verified LPDDR2 and DDR3 Memory Controller designs



PMC-Sierra is now Microsemi

• Semiconductor Manufacturing
• 300 - 400 Employee

• Staff ASIC design/implementation

  • Jun 2009 - Nov 2015

  • Designed sub-system blocks, from specification to RTL coding to pre-layout netlist generation. • Responsible for backend tasks: in charge of backend flows and mentor junior teams. Lead a team to do static timing closure at chip-level • Chip-level integration: connect sub-systems together, generate various vectors such as BSDL vectors, Inter-Connect (IC) vectors, IDDQ vectors, RAMBIST vectors, floorplan, power estimation. Interface with various functional groups: Layout, Package and Substrate, Mixed Signal, Technology Access, CAD, Product Engineering (PE)



XtremeEDA

• Canada
• Semiconductor Manufacturing
• 1 - 100 Employee

• Senior DFT Consultant

  • May 2008 - May 2009

  . Provided DFT and design work to clients such as AMD, Sarance, PMC-Sierra . Prepared DFT training and presentation materials . Provided DFT and design work to clients such as AMD, Sarance, PMC-Sierra . Prepared DFT training and presentation materials



PMC-Sierra is now Microsemi

• Semiconductor Manufacturing
• 300 - 400 Employee

• Product Design Engineer

  • Nov 2000 - Apr 2008

  PMC-Sierra Inc, November 2000 to April 2008 Involved in most aspects of a chip development cycle: planning, front-end RTL design, back-end implementation, chip-level integration, and functional verification. • Designed Telecom System Blocks (TSB), which is the building block of a chip, from specification to RTL coding to pre-layout netlist generation. • Backend implementations involve synthesis, scan insertion and stitching, static timing analysis, formal verification, vector generations and re-simulations, gate-level simulations, gate-level ECO, and post-layout timing closure. • Verifications include writing testbench components and testcases to functionally verify TSBs and higher block-level components. Other tasks are writing and analysis of functional and code coverage