Experience

New Wave Design and Verification

• United States
• Defense and Space Manufacturing
• 1 - 100 Employee

• Director of Product Management

  • Jun 2023 - Present

  Eden Prairie, Minnesota, United States

• Product Line Director-Fibre Channel/ARINC-818/RTPS

  • Apr 2021 - Jun 2023

  Eden Prairie, Minnesota, United States Own the direction of product line under management: set priorities, define product concepts, determine investment required, obtain customer commitments, set pricing, set schedules, manage overall return on investment of the product line. Develop relationships with new and existing customers. Understand the customer needs and develop products that fit their requirements. Manage customer expectations of the product set while securing design wins for the product set. Assess the… Show more Own the direction of product line under management: set priorities, define product concepts, determine investment required, obtain customer commitments, set pricing, set schedules, manage overall return on investment of the product line. Develop relationships with new and existing customers. Understand the customer needs and develop products that fit their requirements. Manage customer expectations of the product set while securing design wins for the product set. Assess the market landscape from both an opportunity and competitor standpoint. Determine places to focus and places to not focus. On a daily basis interact with the sales team on new leads, ongoing proposals, account management, customer feedback, issue resolution, and priority setting. Develop product marketing plans with the marketing team to achieve product introduction and penetration at new accounts. Provide priority, staffing needs, technical expectations, product specifications, and issue/opportunity priority.

• Chief Engineer

  • Aug 2015 - Mar 2021

  Minneapolis, Minnesota, United States Performed FPGA systems engineering, architecture and design development activities. Lead engineer responsible for Fibre Channel controller FPGAs (ASM, SCSI, RDMA, ARINC-818) Responsible for integrating all IP blocks, pinout selection, placement and timing constraints Product owner managing releases of new features and bug fixes Managed implementation of UVM verification environment

• Digital Design and Verification Sr. Staff Engineer

  • Jun 2012 - Jul 2015

  Saint Louis Park, MN Performed marketing, business development, and FPGA architecture development activities for New Wave DV, a start-up division of New Wave Components, specializing in Digital Design and Verification. Lead engineer responsible for 1394b controller investigation in Microsemi flash FPGAs Implemented RTL code of 1394 PHY layer based on IEEE 1394-2008 Lead engineer responsible for Fibre Channel network interface controller FPGA design. Performed 7 months of onsite contract… Show more Performed marketing, business development, and FPGA architecture development activities for New Wave DV, a start-up division of New Wave Components, specializing in Digital Design and Verification. Lead engineer responsible for 1394b controller investigation in Microsemi flash FPGAs Implemented RTL code of 1394 PHY layer based on IEEE 1394-2008 Lead engineer responsible for Fibre Channel network interface controller FPGA design. Performed 7 months of onsite contract services to Micron Technology. Primary responsibility was to aid transition of ASIC verification process to modern functional verification techniques using SystemVerilog and UVM Provided input to verification process based on previous experience and lessons learned Responsible for developing a UVM verification environment to test a 3D stacked DRAM controller Focused on creating reusable verification components shared across projects



Lockheed Martin

• United States
• Defense and Space Manufacturing
• 700 & Above Employee

• Electrical Engineer Sr

  • Nov 2010 - Aug 2012

  Architectural design and VHDL coding of a centralized register/memory block used in a network processing application. Developed an OVM based SystemVerilog simulation environment for a Network Interface Unit which included PCIe and Ethernet interfaces Developed stimulus generators, system models, scoreboards and test cases

• Hardware/Electrical Engineer

  • May 2007 - Oct 2010

  Architected and documented several VHDL modules for FPGA designs including a Fibre Channel core for a Dense Wave Division Multiplexing (DWDM) system and a Transmit function for two Network Interface Units. Gained experience with the following protocols: PCI, PCI-X, PCIe, Fibre Channel, Serial Rapid IO, and Ethernet. Participated in the development of several System Verilog simulation environments using the Advanced Verification Methodology (AVM) and Open Verification Methodology (OVM).

• Hardware Engineer Asc

  • Aug 2005 - Apr 2007

  Participated in simulation verification (System Verilog) of VHDL FPGA designs. Participated in Beta testing of System Verilog support in Mentor Graphic’s tools. Responsible for integrating PCI, PCIe, and Fibre Channel Bus Functional Models (BFM). Responsible for the initial identification/analysis of problems discovered through simulation.



Honeywell

• United States
• Appliances, Electrical, and Electronics Manufacturing
• 700 & Above Employee

• Student Aide - Component Engineering

  • Mar 2003 - Jul 2005

  Assisted in facilitating the standardization, application, and use of purchased parts. Performed tasks related to part selection, sourcing, specification, and use. Supported the acquisition, entry, and processing of part data in component databases.