Experience

Qamcom

• Sweden
• Telecommunications
• 1 - 100 Employee

• System Design Engineer

  • May 2013 - Present

  Consultant assignment at Volvo Cars Cooperation - feasibility study (2022.06-2022.12) - SoC architect - Investigated NoC alternatives and memory bandwidth requirements - Investigated computational requirements - Evaluated vendors for IP-blocks, EDA-tools, design services and silicon foundries. - Supported NPU investigations - Supported pre-silicon SW development investigations - Considered FuSa requirements Ka band OTA radar simulator (2021-2022.06) - Subsystem responsible for the echo generation part of the radar simulator. The team consist of 7 people working with FPGA and SW implementation as well as system level matlab model of the functions. My responsibilities include e.g. task planning and definition, architectural design, risk management and technical studies. Consultant assignment at Huawei Technologies Sweden AB - Göteborg (2016-2021) - Researching CPRI link data rate reduction alternatives - Researching densification alternatives - Project manager backhauling on unlicensed bands research (5 person project) - Project manager Intelligent Reflective Surfaces research (7 person project) Various inhouse assignments including (2013-2016) - Soft link architecture (Solar) research project. Microwave modem implemented on multicore DSP. Matlab model development and C code programming - Radar backend matlab interface. Developed matlab interface to an 8 channel radar backend. Also included some C programming of Nios processor. - High Frequency Trading development project. Technical lead for a 10 person team working with FPGA and SW development as well as system test. The assignment included long term planning of future functions as well as making sure deliveries were made on time. Show less



Ericsson

• Sweden
• Telecommunications
• 700 & Above Employee

• Senior Specialist Embedded DSP

  • Dec 2009 - May 2013

  Part of the DSP subsystem core team. The core team was responsible for the planning of both system design and implementation of the digital signal processing subsystem in a microwave link digital ASIC. The core team was leading a system design and implementation team consisting of about 30 system and design resources.

• Senior digital ASIC Designer

  • Sep 2004 - Dec 2009

  - Contributed to several IPs (implementation proposals) for digital radio implementation for GSM, WCDMA, and LTE mobile standards.- Responsible for the uplink subsystem in WCDMA digital radio ASIC (WARP). Work included ASIC system design (mainly signal processing), work planning and extensive contacts with WCDMA system department.- System design and planning of FPGA for Wimax base station digital radio (project was closed down after 6 month)- Verification of base station digital radio FPGA by simulation and lab measurements. Show less



Loqware Technologies

• Sweden

• System and Hardware Design Engineer

  • Feb 2003 - Aug 2004

  - Continued with the USB hard disc drive project as an employee (started as a consultant from Syntera). - Continued with the USB hard disc drive project as an employee (started as a consultant from Syntera).



Syntera AB

• Sweden
• Computer Hardware Manufacturing
• 1 - 100 Employee

• Senior ASIC and Electronics consultant

  • Nov 2001 - Feb 2003

  - Responsible for hardware and software development of a USB hard disk drive with integrated fingerprint sensor. The development team consisted of 4 design engineers. The work included e.g. project planning, system design, system description, design reviews, and subcontractor contacts. - Participated in several customer and sales meetings and provided technical input to sales quotes. - Evaluated soft core embedded processors for programmable logic. The evaluation focus was Xilinx Microblaze and Altera Nios. Show less



SwitchCore AB

• Sweden

• Research Engineer

  • Dec 2000 - Oct 2001

  - Member of a research group investigating novel methods for copper wire signaling. - Responsible for helping signal processing developers understand the implementation costs for different algorithms. - Responsible for evaluating different ASIC technologies with respect to performance. The evaluation included implementation of DSP building blocks using Verilog and synthesis. - Assisted in system design of a high-speed copper wire signaling system. - Member of a research group investigating novel methods for copper wire signaling. - Responsible for helping signal processing developers understand the implementation costs for different algorithms. - Responsible for evaluating different ASIC technologies with respect to performance. The evaluation included implementation of DSP building blocks using Verilog and synthesis. - Assisted in system design of a high-speed copper wire signaling system.



Saab Ericsson Space

• Sweden

• Design Engineer

  • Aug 1997 - Dec 2000

  - Object manager during the development of an I/O ASIC named COCOS. The number of design engineers varied between 3 and 9. The work included planning, specification and reviews as well as VHDL design of some blocks in the ASIC. To speed up the verification of the ASIC, a prototype board with a Virtex FPGA and a CPU was designed. - Responsible for ASIC synthesis methodologies and the Actel tool suite at Saab Ericsson Space. - Designed and verified the mass memory for the satellite platform PROTEUS. The design phase included PCB schematic entry and FPGA design using VHDL. The FPGA design was verified by simulation and the PCB was verified in the lab. - Designed and verified the FPGAs for the mass memory in the deep space probe ROSETTA. The FPGAs were designed using VHDL and verified by simulation. Show less