Experience

Sintegra Inc.

• United States
• Semiconductor Manufacturing
• 1 - 100 Employee

• Sr. Member of Technical Staff

  • Apr 2017 - Present

  RTL-to-GDSII implementation of ASICs, Physical Verification RTL-to-GDSII implementation of ASICs, Physical Verification



Marvell Semiconductor

• 1 - 100 Employee

• Senior Physical Design / Verification Engineer

  • Mar 2012 - Jan 2017

  * Performed physical design implementation and closed timing in MCMM on blocks using Synopsys ICC in TSMC 28nm technology. * Performed SoC level integration from GDSII using Mentor IC Systems and gdsAssemble flow, generating merged GDSII for tape-out. Taped-out / helped tape-out about 40 designs. * Debugged PG shorts, lvs, antenna, suggesting fixes to physical design team. Traced nets with Cadence Innovus / Encounter and Synopsys ICC. * Checked lvs, drc, erc, xor, and antenna using Mentor Calibre, ensuring they are clean before tape-out. * Edited layouts using AnaGlobe Thunder and Mentor IC Systems. Show less



Synapse Design Automation Inc.

• Physical Design Engineer

  • Aug 2011 - Mar 2012

  * Performed all needed tasks from gate-level verilog netlist to GDSII generation using Magma tools, including floorplanning, timing driven place and route, clock tree generation, RC parasitic extraction, timing closure, drc / lvs / antenna fixes, etc. * Performed timing closure in Magma Talus and Synopsys PTSI. * Checked lvs using Synopsys Hercules and drc using Cadence K2. * Analyzed noises with Cadence / Celtic. * Performed IR drop analyses using Apache / RedHawk, Magma / Quartzrail. * Came up with the MCMM flow for the hardmacros of the project. * Worked with international implementation team. Show less



Magma Design Automation

• United States
• Semiconductors
• 1 - 100 Employee

• Senior Applications Engineer

  • May 2010 - Aug 2011

  * Using latest Talus binary builds, assessing result quality of new builds and generating reports by running regression tests through blocks. * Worked with customers, resolving issues and reporting any tools issues to R&D. * Performed place and route on customer designs that ranged from 300K to about 3M components per block, using TSMC 40nm / 28nm technologies and compared QoR / DRC / Runtime results. * Reviewed and optimized customer’s flow for runtime and performance. * Using latest Talus binary builds, assessing result quality of new builds and generating reports by running regression tests through blocks. * Worked with customers, resolving issues and reporting any tools issues to R&D. * Performed place and route on customer designs that ranged from 300K to about 3M components per block, using TSMC 40nm / 28nm technologies and compared QoR / DRC / Runtime results. * Reviewed and optimized customer’s flow for runtime and performance.



TranSwitch Corporation / Centillium Communications, Inc.

• Staff Engineer, Physical Design

  • Aug 2000 - Sep 2009

  * Performed all needed tasks from gate-level verilog netlist to GDSII generation using Magma tools, including floorplanning, timing driven place and route, clock tree generation, RC parasitic extraction, timing closure, drc / lvs / antenna fixes, and layout editing. * Came up with flows to implement the hardmacros for the TOPs. * Generated Magma library and Simplex extraction library. * Evaluated and correlated Blastnoise with Simplex / Celtic / Primetime. * Checked lvs / drc / antenna / erc / xor using Mentor Calibre. * Worked on SoC and block levels, completing several designs using Magma / Cadence tools on TSMC 0.13LV (130nm) and Chartered 65G (65nm) technologies. * Worked with international design / implementation teams. Show less



Toshiba / Fujitsu / Mitsubishi / Seiko Epson

• Senior Staff EDA Applications Engineer

  • Nov 1984 - Aug 2000

  * Held several positions that supported EDA / ASIC applications. * Resolved customers' technical problems through technical support, including troubleshooting and root cause analysis. * Performed ASIC place and route using Cadence Gate Ensemble and Cadence Cell3 Ensemble. * Held several positions that supported EDA / ASIC applications. * Resolved customers' technical problems through technical support, including troubleshooting and root cause analysis. * Performed ASIC place and route using Cadence Gate Ensemble and Cadence Cell3 Ensemble.