Teck Yunn Lim
Senior R&D Manager, Design Automation at Altera- Claim this Profile
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English Professional working proficiency
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Malay Limited working proficiency
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Chinese Native or bilingual proficiency
Topline Score
Bio
Mark Yeoh
I worked under Teck Yunn during my tenure at Altera from junior engineer all the way to senior engineer. Throughout this period, Teck Yunn never failed to guide and managed me while making me feel more as a friend than just a subordinate. It was an honour to work under his guidance and purview and all his subordinates should be lucky to have a manager who is a born manager..
Xi Jiang
Teck Yunn is a veteran in IC design. He always works on latest technologies and provides insight on the industry. It is amazing that he can always find solutions in the complicated problem involved design, CAD support, foundries and EDA partners.
Mark Yeoh
I worked under Teck Yunn during my tenure at Altera from junior engineer all the way to senior engineer. Throughout this period, Teck Yunn never failed to guide and managed me while making me feel more as a friend than just a subordinate. It was an honour to work under his guidance and purview and all his subordinates should be lucky to have a manager who is a born manager..
Xi Jiang
Teck Yunn is a veteran in IC design. He always works on latest technologies and provides insight on the industry. It is amazing that he can always find solutions in the complicated problem involved design, CAD support, foundries and EDA partners.
Mark Yeoh
I worked under Teck Yunn during my tenure at Altera from junior engineer all the way to senior engineer. Throughout this period, Teck Yunn never failed to guide and managed me while making me feel more as a friend than just a subordinate. It was an honour to work under his guidance and purview and all his subordinates should be lucky to have a manager who is a born manager..
Xi Jiang
Teck Yunn is a veteran in IC design. He always works on latest technologies and provides insight on the industry. It is amazing that he can always find solutions in the complicated problem involved design, CAD support, foundries and EDA partners.
Mark Yeoh
I worked under Teck Yunn during my tenure at Altera from junior engineer all the way to senior engineer. Throughout this period, Teck Yunn never failed to guide and managed me while making me feel more as a friend than just a subordinate. It was an honour to work under his guidance and purview and all his subordinates should be lucky to have a manager who is a born manager..
Xi Jiang
Teck Yunn is a veteran in IC design. He always works on latest technologies and provides insight on the industry. It is amazing that he can always find solutions in the complicated problem involved design, CAD support, foundries and EDA partners.
Credentials
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Innovation Games ® Certified Collaboration Architect
The Innovation Games CompanyAug, 2013- Oct, 2024
Experience
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Altera
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United States
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Semiconductors
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700 & Above Employee
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Senior R&D Manager, Design Automation
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Mar 2009 - Present
Spearheaded DA in initializing and driving R&D’s Global IP-Product Spiral Development Design Methodology at 28nm, received Altera corporate-level Champion of Change awardProject management – Global DA lead roles into the Stratix 10, Max 10, and Hardcopy Pro flow/library developmentOrganizational development – workforce transformation that had retargeted >40% of team members into focusing on cell-based design automationWas scored 3.75/4.0 in Manager Performance Feedback by the teamEstablished cell-based DA and R&D Infrastructure team, focusing on 5 key coverage areas of cell-based design flows, library and infrastructure- Electrical and Power Analysis- Design Implementation- Design Verification and Analysis- Standard cell and Foundation IP libraries- R&D InfrastructureManaged the team to deliver converged methodologies/flows for 55nm/40nm/28nm/20nm CPLDs/FPGAs/SoCs/Structured ASICs in collaboration with Design team- RTL2GDS- Transistor-level STA and timing modeling- Constraint generation and verification- RTL Linting and CDC solutions- Custom IP Formal Verification solutions- Design Intent- PDN, RV and power planning solutions based on Apache Redhawk/Totem- ICD Build/Release and Silicon Revision Issue Tracking- Physical compliancy guideline/enforcement solutions- ASIC-Custom bridging solution and compliancy guidelines- ASIC sign-off flow- Structured Array IP (SAIP) library and memory compiler developmentPartnered with IT on Altera Engineering Resource Optimization (AERO) initiative by the Engineering Infrastructure Office, responsible for tool profiling and license/hardware optimization of 8/10 top EDA tools by spending, resulted in overall compute farm efficiency of >25% and cost savings in the range of hundreds of thousand USDEstablished DA Steering Council- Curb “Bad” DA deliverables- Evolve meeting format into DA POR communication and review- Establish scorecard system for DA deliverables
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Supervising Member of Technical Staff, CAD
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May 2001 - Mar 2009
Project management and technical leadership - DA Technical lead into Hardcopy Structured ASIC design flows and customer conversion flow development- Functional/timing/power modeling- In-house tools enabled Altera’s unique competitive advantage in the Structured ASIC market segment with Hardcopy II/III/IV lines of products- Streamlined Hardcopy customer design conversions under tight RTL-to-GDS2 scheduleCollaborated with Design on Structured ASIC logic cell architecture definition and cell library creation- Rapid prototyping capability without actual physical implementation whilst considering logic efficiency and routing architecture- Cell library generation from boolean equations or BDD representations into programmed netlists, correct-by-construction layout, functional/timing/power libraries and various library viewsEstablished ASIC and standard cell library support capability and direct engineer-to-engineer interface to foundry partner- Standard cell characterization, performance/power assessment and design view generation- Provided solutions on Physical database preparation, embedded MRAM timing modeling and custom layout construction guidelines and requirementsRCE/Power Analysis tools’ support and development- Runset creations, updates and job submitter- Process setup, benchmark and fine-tune- Methodology definition/refinement and tool bug workarounds- Chip-level LVS/RCE/Power Analysis debugPhysical Verification support and development- Runset creations/updates for LVS, RCE, Power analysis- Hercules/Calibre DRC support- Mask algorithm, SVS/LVL- Runset release QA suite and methodology- Lead Calibre DRC deployment and Calibre LVS evaluation - Calibre rule deck coding guidelines - Calibre DRC rule deck coding - Qualified, optimized and released foundry's rule deckPioneered and collaborated with IT to deploy LSF queue managementEstablished Transistor-level STA (NanoTime) support and development capability in Altera
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Education
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2008 - 2010
University of Ballarat
Master of Business Administration (MBA), Business Administration, Management and Operations -
1998 - 2001
Multimedia University
Bachelor of Engineering (B.Eng.), Computer Engineering -
1991 - 1995
Chong Hua High School, Seremban
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