Experience

Siliconova

• Bangladesh
• Semiconductor Manufacturing
• 1 - 100 Employee

• IC Layout Design Engineer - II

  • Mar 2023 - Present

• IC Layout Design Engineer - I

  • Oct 2022 - Feb 2023

• Trainee Engineer

  • Jul 2022 - Sep 2022

  SILICONOVA LIMITED engaged in the design, packaging & testing, fabrication, and Manufacturing of semiconductors and semiconductor devices, such as Central Processing Unit (CPU), Microprocessor (MCU), RISC and RISC-V Processors, AI and Knowledge-based Processors, Memory, RAM, Storage, SSD, Ethernet, transistors, integrated circuits (IC), Application Specific Integrated Circuit (ASIC), System on Chip (SOC), Field programable Gate Array (FPGA) and Microchips for Computer Motherboard, Data Center Electronics Devices, IoT and IIoT Devices, Wireless, Mobile, Networking, Wi-Fi, Small Cells, Wireless Power, Augmented Reality, Location Services, Automotive, 5G, PC computing. We devote ourselves to developing high-performance/low-power 32/64 bit processors and their associated SoC to serve the rapidly growing embedded system applications worldwide. Show less



TAHOE

• United International University

• IC Mask Design

  • Feb 2022 - Jun 2022

  • Learned the basic concept of Linux Command, Electronics and Basic Circuits • Introduced of Cadence Tools for circuit Layout • Learned the schematic design, simulation and analysis • Learned the circuit design techniques(Placement,routing and matching) • Designed analog and digital layout • Designed practical application of analog and digital layout and physical verification (LVS,DRC,ERC,EM,IR) -- Placement Techniques -- Finger & Multiplier -- Matching Techniques -- Routing Techniques -- Latchup issue & prevention -- Antenna Effect & prevention -- Electromigration Effect -- IR Drop & prevention -- Cross-Talk & prevention -- Shielding Techniques Show less



IEEE UIU Student Branch

• Non-profit Organizations
• 1 - 100 Employee

• VLSI Design (Layout)

  • Sep 2019 - Sep 2019

  --- Three days VLSI Design Training Organized by IEEE UIU Student Branch --- Learned Basic circuit design using CMOS --- Schematic Design --- Layout Design --- Physical Verification (LVS, DRC) --- Three days VLSI Design Training Organized by IEEE UIU Student Branch --- Learned Basic circuit design using CMOS --- Schematic Design --- Layout Design --- Physical Verification (LVS, DRC)