Tai Zu Jie
Senior Engineer at 4ASICs- Claim this Profile
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Bio
Experience
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4ASICs
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Malaysia
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Design
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1 - 100 Employee
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Senior Engineer
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Jan 2022 - Present
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Physical layout designer
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Feb 2017 - Jun 2019
Performed a wide IC design mask design including digital & analogue layout. Experienced with high end process etc. 40nm,28nm,10nm, 7nm. Performed a wide IC design mask design including digital & analogue layout. Experienced with high end process etc. 40nm,28nm,10nm, 7nm.
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Design Engineer
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Dec 2015 - Jan 2017
Performed CAD/PCB layout designs for 20+ PCB projects using Altium designer software that includes:- HAST(High Accelerated Stress Test) boards for IC stress test.-HTOL (High Temperature Operating Life) boards with fine pitch 0.7mm BGA components socket.-High sensitivity analogue device boards and responsible to the power delivery and ground structures design.Fully responsible for converting design schematics into actual board layout for PCB fabrication that includes:• Translating of mechanical AutoCAD file into mechanical outline/layer in Altium software• Model partial schematic (given by clients) to full schematics in Altium software• Full PCB CAD layout implementation of schematics• PCB layout design review with customers • Generate stencil file for manufacturing pick & place• Developing test plan & test jig for board testing in manufacturing• BOM (Bill of Material) creation & component research/recommendation
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Education
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Universiti Tunku Abdul Rahman
Bachelor of Engineering (B.Eng.), Electronics Engineering