Sébastien Tiran

SCA domain responsible at SGS Brightsight
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Contact Information
us****@****om
(386) 825-5501
Location
Delft, South Holland, Netherlands, NL
Languages
  • Français Native or bilingual proficiency
  • Anglais Full professional proficiency
  • Espagnol Elementary proficiency
  • Néerlandais Elementary proficiency

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Experience

    • Netherlands
    • IT System Testing and Evaluation
    • 100 - 200 Employee
    • SCA domain responsible
      • Feb 2022 - Present

    • Senior security evaluator
      • Jan 2021 - Present

    • SCA R&D coordinator and evaluator
      • Jan 2019 - Present

    • Side Channel security evaluator and developer
      • Mar 2015 - Present

      - Side Channel security evaluator.- Developer (developing and maintaining tools for SCA in languages such as MATLAB, Java, Python).

    • France
    • Research Services
    • 1 - 100 Employee
    • Postdoc in security of cryptographic systems
      • Jan 2014 - Dec 2014

      Postdoc (1 year) done at CMP (Centre de Microélectronique de Provence) of Gardanne, within the team SAS (Systems and Secure Architectures). ▫ Development of advanced attacks by analysis of electromagnetic emissions. ▫ Research and use of statistical tools in order to study the activity of cryptographic devices with the analysis of electromagnetic emissions. Postdoc (1 year) done at CMP (Centre de Microélectronique de Provence) of Gardanne, within the team SAS (Systems and Secure Architectures). ▫ Development of advanced attacks by analysis of electromagnetic emissions. ▫ Research and use of statistical tools in order to study the activity of cryptographic devices with the analysis of electromagnetic emissions.

    • PhD student in security of cryptographic systems
      • 2010 - 2013

      Thesis done at LIRMM under the direction of Philippe Maurine. Thesis in: Methods of advanced attacks of cryptographic devices by analysis of electromagnetic emissions. Themes: ▫ Side Channel Attacks in the frequency domain. ▫ Leakage model in the frequency domain of cryptographic devices. ▫ Impact of filtering power traces or electromagnetic emissions on Side Channel Attacks Development: ▫ C programming of new and existing Side Channel Attacks. ▫ Programming in QT of an interface to launch the various attacks developed. Show less

    • Defense and Space Manufacturing
    • 1 - 100 Employee
    • Internship, programming and testing of Timing Attacks
      • Mar 2010 - Aug 2010

      Internship graduation at DGA-MI, Rennes. (6 months) Topic: Study of implementation flaws (AES open SSL) on different systems / computers, Timing Attacks. Development: C programming of Timing Attacks on C implementations of the AES. Internship graduation at DGA-MI, Rennes. (6 months) Topic: Study of implementation flaws (AES open SSL) on different systems / computers, Timing Attacks. Development: C programming of Timing Attacks on C implementations of the AES.

Education

  • LIRMM
    PhD, Embedded Security (Side Channel Attacks)
    2010 - 2013
  • Polytech Montpellier
    Engineering degree (Master degree), Polytech School Montpellier section Robotics Electronics and Industrial Computing
    2007 - 2010
  • Lycée Carnot de Dijon
    Cycle préparatoire MP
    2005 - 2007

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