Experience

AltCognito Systems

• India
• Semiconductor Manufacturing
• 1 - 100 Employee

• Physical Design Engineer

  • Sep 2021 - Present



VLSIGuru Training Institute

• India
• E-Learning Providers
• 100 - 200 Employee

• Physical Design Engineer Trainee

  • Jan 2019 - Jun 2019

  Role: Design-Import, sanity Checks, Floor plan, Power plan, Placement, Timing optimization, CTS, Routing, timing Analysis, LVS&DRCResponsibilities:• Imported verilog netlist, read SDC, TLU+ file and linked physical library• Performed sanity checks• Floor plan: Estimate the area of the chip and aspect ratio, Placed macros and fixed macros, created the keep out margin & blockages over macros, Pin placement was done with help of guidelines given by top level, derived PG connection.• Placement: Assigning correct position to standard cells on the chip with noOverlapping, applied various strategies to control congestion• CTS: Built the clock tree by using inverters and buffers for balancing skew.• Routing: In this connect all the cells physically with the metal straps• RC Extraction using STARRC and Fixed trans, cap and timing violation in PRIMETIME.