Sukanthi Thotakura

Design Verification Engineer at TES Electronic Solutions GmbH
  • Claim this Profile
Contact Information
us****@****om
(386) 825-5501
Location
DE
Languages
  • English Full professional proficiency
  • Hindi Native or bilingual proficiency
  • Telugu Native or bilingual proficiency
  • German Elementary proficiency

Topline Score

Topline score feature will be out soon.

Bio

Generated by
Topline AI

5.0

/5.0
/ Based on 2 ratings
  • (2)
  • (0)
  • (0)
  • (0)
  • (0)

Filter reviews by:

Dr.-Ing. Matthias Gruenewald

Sukanthi was supporting us for one year on several topics. She verified a MIPI CSI-2 receiver for our RH850 radar processor and a debug circuit for our R-Car SoC. On top of that, she also designed a LVDS to MIPI converter for an FPGA board, including synthesis and timing closure. And she also helped us with explaining complex technical topics to our customers. Sukanthi is very motivated and is very quick in learning new topics. For example, she mastered the LVDS to MIPI converter including design, verification, synthesis and static timing analysis. Her favorite topic is verification of digital circuits. In addition, she is a very good communicator, since she had to deal with different people in Japan, India, and Germany. It was a pleasure working with Sukanthi and I wish her all the best for the future!

Durga Pavani B

Sukanthi is focused, highly motivated, and talented person. She is also very popular and well know for her wide range of talents like Singing, Painting, event management, and Dancing. With her unique talents Sukanthi will be a valuable asset to any team.

You need to have a working account to view this content.
You need to have a working account to view this content.

Experience

    • Semiconductor Manufacturing
    • 100 - 200 Employee
    • Design Verification Engineer
      • Jun 2017 - Present

      ▪ Pre-Silicon Functional Verification of IPs for a Radar Digital Core ▪ SVA checkers to enforce protocol check ▪ Regression analysis and Assessment of Code Coverage & Functional Coverage ▪ Generate Product Verification Report (PVR) and Release notes ▪ Develop various automation scripts using PERL ▪ Firmware unit testing of a Radar MMIC – Unit test cases in C to verify FW unit as per SW requirements managed in JAMA ▪ Firmware Integration testing of a Radar MMIC – verification of FW unit integration according to Software Architectural Design (SWA) ▪ UVM sequences/testcases to verify each FW unit and/or state ▪ UVM testbench verification of SPI Interconnect ▪ Verification and Checkers for IPs in Automotive Instrument Cluster 2020 (FPGA) using VHDL

    • Japan
    • Semiconductor Manufacturing
    • 700 & Above Employee
    • Project Engineer
      • Nov 2015 - May 2017

      ▪ Part of Global Advanced Driver Assistance Systems (ADAS) Team ▪ Involved in RADAR and Renesas R-Car Projects ▪ UVM test bench for an IP from scratch and Coverage, Scoreboard implementation ▪ Validation of MIPI-CSI2 Testbench ▪ Design an IP spec that increased packet efficiency by 50% ▪ Design FPGA - Interface between MMIC and MIPI-CSI2 with LVDS interface ▪ UVM verification testbench enhancement and testcases for Apical Image Signal Processor ▪ Part of Global Advanced Driver Assistance Systems (ADAS) Team ▪ Involved in RADAR and Renesas R-Car Projects ▪ UVM test bench for an IP from scratch and Coverage, Scoreboard implementation ▪ Validation of MIPI-CSI2 Testbench ▪ Design an IP spec that increased packet efficiency by 50% ▪ Design FPGA - Interface between MMIC and MIPI-CSI2 with LVDS interface ▪ UVM verification testbench enhancement and testcases for Apical Image Signal Processor

    • India
    • Semiconductors
    • 1 - 100 Employee
    • Engineer - VLSI ASIC Verification
      • Jul 2013 - Oct 2014

    • United States
    • Semiconductor Manufacturing
    • 700 & Above Employee
    • SOC Verification Engineer
      • Oct 2010 - Jun 2013

      ▪ IP Verification/Debug of x86 CPU based on AMD’s Fusion architecture with high-performing CPU cores and cutting-edge Graphics IP on a single die ▪ SoC Gate Level Simulation for a four Core x86 CPU ▪ Regressions on pre-netlist and post-netlist simulations ▪ IP Verification/Debug of x86 CPU based on AMD’s Fusion architecture with high-performing CPU cores and cutting-edge Graphics IP on a single die ▪ SoC Gate Level Simulation for a four Core x86 CPU ▪ Regressions on pre-netlist and post-netlist simulations

    • Higher Education
    • 700 & Above Employee
    • Graduate Teaching Assistant
      • Aug 2008 - Jul 2010

      Assisting the undergraduate students in the lab to design a Slone Audio Amplifier using OrCAD Capture software and implementation of the same on a PCB. Assisting the undergraduate students in the lab to design a Slone Audio Amplifier using OrCAD Capture software and implementation of the same on a PCB.

Education

  • Mississippi State University
    Master of Science (M.S.), Electrical and Computer Engineering
    2008 - 2010
  • Gandhi Institute of Technology & Management (GITAM) University, Visakhapatnam
    Bachelor of Engineering (B.E, Electronics and Communications Engineering
    2004 - 2008

Community

You need to have a working account to view this content. Click here to join now