Experience

Altera

• United States
• Semiconductors
• 700 & Above Employee

• Verification Lead

  • Feb 2011 - Present

  Lead the definition, architecture and implementation of a coverage-driven verification environment implemented with OVM/VMM and assertions. - Develop DV schedule and allocate resources appropriately according to design requirements - Develop comprehensive test plan and continuously measure progress against the plan throughout the project. - Verify blocks and chip level using assertion-based verification, formal analysis, and randomized test generation. - Design and develop testbench components such as BFM and verification tools. - Perform RTL code coverage, assertion coverage, and gate level simulations. - Define and design verification regression environment. - Drive and oversee new verification tools and flows for efficiency improvements - Mentor junior engineers on project execution and career development. Show less



Bay Microsystems, Inc.

• United States
• IT Services and IT Consulting
• 1 - 100 Employee

• Manager, VLSI Software Development

  • Mar 2009 - Feb 2011

  Manage a development team responsible for:- Architecture modeling with System-C- Module RTL verification with modelsim, vcs, axiom simulator- Device Driver API development in C and C++- ASIC bring-up support for Serdes/Interface calibration software- Develop ASIC validation test plan- SONET/OTN standard compliance testing with JDSU ONT and IXIA tester- Support system group in bring-up of ASIC for system-level software integration- Support and train FAE and customer- Manage project schedule and resources with Microsoft Project Show less

• Senior VLSI Engineer

  • Apr 2001 - Mar 2009

  40 Gigabit SONET/OTN Framer/Mapper Transport Processor:- Designed and implemented the SONET STS768c Sonet Mapper - Synthesizing the RTL code on TSMC 65nm technology library- Perform formal verification with Cadence Conformal- Generate testvector for ATE Testing40 Gigabit Network Processor:- Developed SPI5 Functional Models in C++ and verified the SPI5 RTL implementation- Developed CAM based Classification Functional Models in C++ and verified the Classification Module RTL implementation- Integrated vendor CAM System-C model into full chip functional model and full chip rtl verification environment- Validate chip function with sprient testcenter on hardware development kitOC192 Gigabit Network Processor:- Formulate functional testplan for Chip level verification- Design chip level verification testbench- Create Perl scripts for verifying test results- Setup Environment for code Coverage using VCS Covermeter- Generate test vector for chip bring-up- Model SPI41 framer for testing overflow/under-run conditionOC-48 Gigabit Network Processor:- Create Architecture Specification for Classifying Unit- Responsible for RTL coding of TCAM/SRAM based classifying Unit- Create OVA Assertions for UnitOC-192 Classifying Engine:- Testing of SPI42 Dynamic training sequence- Verify Packet Policing Function- Performance matrix generation Show less



Synopsys

• Senior CAE

  • 1999 - 2001



Lockheed Martin

• United States
• Defense and Space Manufacturing
• 700 & Above Employee

• ASIC Engineer

  • 1996 - 1997



IBM

• United States
• IT Services and IT Consulting
• 700 & Above Employee

• Engineer

  • 1995 - 1996