Steve Koubek
Sr. ASIC Design Engineer at Radiance Technologies- Claim this Profile
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Bio
Gale Shallow
I have had the privilege of working with Steve for the past ten years - first as a co-worker at Scientific Atlanta/CISCO in Lawrenceville and later as his manager at ST Microelectronics also in Lawrenceville. . Steve was an important member of our DOCSIS MAC ASIC IP development with several key roles. Steve developed and integrated the system bus structures used to connect the MAC IP to DDR and other components in the set top and gateway SOCs the MAC was used in. This involved working with the MAC architecture and RTL teams to understand the requirements and specify the bus architecture, generating the bus IP, instantiating it in the MAC, and verifying the correct integration and implementation. In addition Steve took on the role of generating deliveries of the IP to the implementation team that integrated the IP in the SoC. This involved running several tools including Spyglass, synthesis, dft, tetramax, and formal, working with the RTL team to resolve any errors or problems and insuring that the IP met the quality requirements set by the SoC implementation team. Additionally Steve contributed to the verification and test-case development for some components of the DOCSIS IP . Steve demonstrated a willingness to take on new challenges, to learn new tools, and to take ownership of key pieces of the project. The development of the MAC was done on an aggressive schedule and RTL changes were happening often as the project progressed; Steve showed great flexibility and dedication in working with these changes and timelines when the delivery flow had to be restarted - often kicking off processes late on Friday and working through the weekends to insure that the process would continue and that deliveries could be made on time. His dedication to the project helped insure we met our timelines with high quality IP.
Gale Shallow
I have had the privilege of working with Steve for the past ten years - first as a co-worker at Scientific Atlanta/CISCO in Lawrenceville and later as his manager at ST Microelectronics also in Lawrenceville. . Steve was an important member of our DOCSIS MAC ASIC IP development with several key roles. Steve developed and integrated the system bus structures used to connect the MAC IP to DDR and other components in the set top and gateway SOCs the MAC was used in. This involved working with the MAC architecture and RTL teams to understand the requirements and specify the bus architecture, generating the bus IP, instantiating it in the MAC, and verifying the correct integration and implementation. In addition Steve took on the role of generating deliveries of the IP to the implementation team that integrated the IP in the SoC. This involved running several tools including Spyglass, synthesis, dft, tetramax, and formal, working with the RTL team to resolve any errors or problems and insuring that the IP met the quality requirements set by the SoC implementation team. Additionally Steve contributed to the verification and test-case development for some components of the DOCSIS IP . Steve demonstrated a willingness to take on new challenges, to learn new tools, and to take ownership of key pieces of the project. The development of the MAC was done on an aggressive schedule and RTL changes were happening often as the project progressed; Steve showed great flexibility and dedication in working with these changes and timelines when the delivery flow had to be restarted - often kicking off processes late on Friday and working through the weekends to insure that the process would continue and that deliveries could be made on time. His dedication to the project helped insure we met our timelines with high quality IP.
Gale Shallow
I have had the privilege of working with Steve for the past ten years - first as a co-worker at Scientific Atlanta/CISCO in Lawrenceville and later as his manager at ST Microelectronics also in Lawrenceville. . Steve was an important member of our DOCSIS MAC ASIC IP development with several key roles. Steve developed and integrated the system bus structures used to connect the MAC IP to DDR and other components in the set top and gateway SOCs the MAC was used in. This involved working with the MAC architecture and RTL teams to understand the requirements and specify the bus architecture, generating the bus IP, instantiating it in the MAC, and verifying the correct integration and implementation. In addition Steve took on the role of generating deliveries of the IP to the implementation team that integrated the IP in the SoC. This involved running several tools including Spyglass, synthesis, dft, tetramax, and formal, working with the RTL team to resolve any errors or problems and insuring that the IP met the quality requirements set by the SoC implementation team. Additionally Steve contributed to the verification and test-case development for some components of the DOCSIS IP . Steve demonstrated a willingness to take on new challenges, to learn new tools, and to take ownership of key pieces of the project. The development of the MAC was done on an aggressive schedule and RTL changes were happening often as the project progressed; Steve showed great flexibility and dedication in working with these changes and timelines when the delivery flow had to be restarted - often kicking off processes late on Friday and working through the weekends to insure that the process would continue and that deliveries could be made on time. His dedication to the project helped insure we met our timelines with high quality IP.
Gale Shallow
I have had the privilege of working with Steve for the past ten years - first as a co-worker at Scientific Atlanta/CISCO in Lawrenceville and later as his manager at ST Microelectronics also in Lawrenceville. . Steve was an important member of our DOCSIS MAC ASIC IP development with several key roles. Steve developed and integrated the system bus structures used to connect the MAC IP to DDR and other components in the set top and gateway SOCs the MAC was used in. This involved working with the MAC architecture and RTL teams to understand the requirements and specify the bus architecture, generating the bus IP, instantiating it in the MAC, and verifying the correct integration and implementation. In addition Steve took on the role of generating deliveries of the IP to the implementation team that integrated the IP in the SoC. This involved running several tools including Spyglass, synthesis, dft, tetramax, and formal, working with the RTL team to resolve any errors or problems and insuring that the IP met the quality requirements set by the SoC implementation team. Additionally Steve contributed to the verification and test-case development for some components of the DOCSIS IP . Steve demonstrated a willingness to take on new challenges, to learn new tools, and to take ownership of key pieces of the project. The development of the MAC was done on an aggressive schedule and RTL changes were happening often as the project progressed; Steve showed great flexibility and dedication in working with these changes and timelines when the delivery flow had to be restarted - often kicking off processes late on Friday and working through the weekends to insure that the process would continue and that deliveries could be made on time. His dedication to the project helped insure we met our timelines with high quality IP.
Experience
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Radiance Technologies
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United States
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IT Services and IT Consulting
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1 - 100 Employee
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Sr. ASIC Design Engineer
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May 2021 - Present
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Invariant Corporation
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United States
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Software Development
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1 - 100 Employee
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Sr. Engineer
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May 2016 - May 2021
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Sr Hardware Design Engineer
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May 2001 - 2016
ASIC Design Engineer on ASICs for digital set-top boxes, involved in most aspects but primarily RTL design, IP integration, verification and IP delivery. My team successfully completed all the design projects within cost and schedule. These designs have been integrated into millions of products worldwide.-Packaging of Docsis3.1 IP for delivery to the back-end team for place and route. Responsibilities included final RTL checks using Spyglass, BIST insertion, synthesis, constraints generation, test insertion, test pattern generation, timing analysis and formal verification. This also involved significant communication with other team members to resolve timing and congestion issues, as well as addressing all RTL specific concerns.-Responsible for designing the system bus architecture for several ASICs and IP including a 50 million gate Docsis headend ASIC, a Docsis3.1 and Docsis3.0 IP. This encompassed Memory Map development, RTL generation and development, simulation, verification and documentation. Additional responsibilities include bus architecture development of FPGA prototype SOC platforms.-Responsible for assisting with testbench development for many of our ASICs and IP. This also included writing several detailed tests for verification of sub-modules and the top-level system.-Verification of complex IP using Cadence’s Vmanager. Responsibilities included developing tests for the verification of a Docsis3.0 multi-channel upstream/downstream and used functional coverage as a “completion” metric.-Responsible for the integration and testing of key IP components for the video pipeline in our set-top box ASICs. This included dual H.264/MPEG-4 video decoders, ARM Mali graphics core and Blitter functions. The video decoders and ARM graphics core had multiple embedded processors.
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Lockheed Martin
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United States
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Defense and Space Manufacturing
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700 & Above Employee
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Senior R&D Engineer
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Oct 1993 - May 2001
Primary responsibilities included research and development of new technologies, architectural and logic design, simulation, test and characterization of Very Large Scale Integrated (VLSI) circuits required for high speed/low cost space and ground systems.-Lead Hardware Engineer for next generation all-digital 600 Mbps receiver. Responsibilities included the design of a 5 million transistor .35 micron ASIC. The chip demodulates BPSK and QPSK data at rates up to 600 Mbps. Assisted in the design of a 1.2 GHz GaAs Multiplexer ASIC and a high rate Viterbi decoder ASIC capable of data rates up to 300 Mbps. Responsible for simulating these three ASICs as a system and integrating them on a PCI compatible card to complete the receiver system. Responsible for coordinating the implementation and development of the algorithms into actual hardware elements and for prototyping these algorithms in hardware using FPGAs. -Lead Hardware Engineer for the ACD (ATM Conversion Device) project. The system allows ECL and RS-422 end to end data transmission across an ATM network. Responsibilities included design and development: handling all hardware related issues with the project; leading and coordinating the system integration and software tasks. Designed a Motorola 68030 based VME card to provide the ECL and RS-422 serial interface to the ATM network.-Designed a Multichip Module utilizing an Anti-Fuse technology substrate. This work included not only the design of the circuit but also the research and evaluation of different MCM technologies and vendors to select those best suited for the application.-Designed a Motorola 68030 CPU Mezzanine board. The board is used as an embedded processor on motherboard designs which need real-time processing capabilities. -Member of the Hardware Environment Group. This group handles all hardware-related issues including the continual improvement of the entire in house design environment and the evaluation and upgrades of new design tools.
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Westinghouse Electric Corporation
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United States
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Manufacturing
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1 - 100 Employee
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Design Engineer
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Aug 1989 - Oct 1993
Responsible for the design, simulation, documentation and testing of digital circuit boards and FPGAs for radar applications. Also responsible for firmware development to process sonar image data. Responsible for the design, simulation, documentation and testing of digital circuit boards and FPGAs for radar applications. Also responsible for firmware development to process sonar image data.
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Education
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University of Nebraska-Lincoln
Bachelor of Science (BS), Electrical and Electronics Engineering
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