Stephane Gagnon
R&D and tech. support at Énergie Volthium inc- Claim this Profile
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Bio
Francis Chayet
I worked several years with Stéphane, I know Stéphane as a friend and as a colleague. Always available to help colleagues from any department He is extremely flexible and proactive, dedicate to his work, can take the lead of a project and deliver on time.
Francis Chayet
I worked several years with Stéphane, I know Stéphane as a friend and as a colleague. Always available to help colleagues from any department He is extremely flexible and proactive, dedicate to his work, can take the lead of a project and deliver on time.
Francis Chayet
I worked several years with Stéphane, I know Stéphane as a friend and as a colleague. Always available to help colleagues from any department He is extremely flexible and proactive, dedicate to his work, can take the lead of a project and deliver on time.
Francis Chayet
I worked several years with Stéphane, I know Stéphane as a friend and as a colleague. Always available to help colleagues from any department He is extremely flexible and proactive, dedicate to his work, can take the lead of a project and deliver on time.
Experience
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Volthium Energy inc.
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Canada
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Renewable Energy Semiconductor Manufacturing
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1 - 100 Employee
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R&D and tech. support
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Oct 2022 - Present
LiFePO4 : Lithium Fer Phosphate batteries LiFePO4 : Lithium Fer Phosphate batteries
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Akka Technologies
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Belgium
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Information Technology & Services
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700 & Above Employee
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FPGA/ASIC DSP Designer (VHDL), Aerospace
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Apr 2021 - Oct 2022
Algorithms Implementation in VHDL for ASIC / FPGA in Aerospace domain Algorithms Implementation in VHDL for ASIC / FPGA in Aerospace domain
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Octasic
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Canada
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Telecommunications
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100 - 200 Employee
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4G-LTE/5G PHY-DSP (OFDM)
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Aug 2018 - Apr 2021
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Senior ASIC Designer
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Apr 2017 - Aug 2018
- VHDL design of functional blocks and complete device- IP configuration and integration- Creation of technical documentation for internal, Foundry, and/or Customer use.- Formal Verification : Synopsys Formality * RTL to Gate * RTL to RTL * Gate to Gate- ECO flow- Linux environment
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OPAL-RT TECHNOLOGIES
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Canada
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Software Development
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200 - 300 Employee
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Spécialiste concepteur & Chargé de Projet FPGA / Designer & Project Leader FPGA
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May 2016 - Apr 2017
Real-Time processing / simulationAlgorithm FPGA : Xilinx 7th Series (Kintex 7, Zynq, Virtex 7)Tools: - Xilinx, Vivado 2015.3 and up - Xilinx System Generator (XSG) - Xilinx ISE 14.7Architecture tool : MagicDrawHigh Speed Link : Transceivers : GTX, GTH Protocol : Aurora Physical Link : SFP Fiber Optic Sync counter/timer : IEEE-1588Revision tool : CVS, GITArchitecture tool : MagicDrawBug tracking tool : JiraAgile tracking tool : Confluence
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Averna
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Canada
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Appliances, Electrical, and Electronics Manufacturing
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300 - 400 Employee
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Senior DSP VHDL Designer (FPGA) & Architech OFDM
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Feb 2014 - May 2016
Docsis 3.1 (OFDM, OFDMA) : PHY Architecture and DesignFPGA : Xilinx Kintex 7 FamilyTools: - Xilinx, Vivado 2014.2 and up - Aldec, Riviera-Pro Revision tool : SVNProtocol : DocSis 3.1 (similar to DVB-C2, S2)Technology : PHY (OFDM, OFDMA) Docsis 3.1 (OFDM, OFDMA) : PHY Architecture and DesignFPGA : Xilinx Kintex 7 FamilyTools: - Xilinx, Vivado 2014.2 and up - Aldec, Riviera-Pro Revision tool : SVNProtocol : DocSis 3.1 (similar to DVB-C2, S2)Technology : PHY (OFDM, OFDMA)
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Multi DSP Custom ASIC, "C" language programmation
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Feb 2008 - Apr 2009
Telecom Algorithm implementation in "C" code for "XG-PHS/Japanees" protocolDSP core Coolflux Telecom Algorithm implementation in "C" code for "XG-PHS/Japanees" protocolDSP core Coolflux
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Senior FGPA/ASIC VHDL Designer (DSP) OFDM
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Feb 2001 - Feb 2008
Four different ASICs in 8 years.Relationship with different Fabs.Bridge between backend and verification team.VHDL Designer : Telecom Algo Four different ASICs in 8 years.Relationship with different Fabs.Bridge between backend and verification team.VHDL Designer : Telecom Algo
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associé
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2006 - 2008
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R&D Engineer (Robotics)
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Sep 1992 - Feb 2001
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Research Engineer
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Sep 1992 - Feb 2001
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Stagiaire (Bac en ingénierie)
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Jan 1990 - Sep 1990
Military environnementTesting of ADATS system (Air Defence Anti Tank System)* Laser guidance missile testing* Radar testing* Hydraulic control testing Military environnementTesting of ADATS system (Air Defence Anti Tank System)* Laser guidance missile testing* Radar testing* Hydraulic control testing
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Education
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Université du Québec - Ecole de Technologie supérieure
Bac en ingénierie (Engineering), ASIC/VLSI VHDL (Telecom) -
Cegep Montmorency
Technician, Electronics / Micro-Processor, Telecom