Stefano Mainolfi

MNAND Validation Engineer at Micron Semiconductors
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Contact Information
us****@****om
(386) 825-5501
Location
Avellino, Campania, Italy, IT

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Experience

    • United States
    • Financial Services
    • 100 - 200 Employee
    • MNAND Validation Engineer
      • Apr 2010 - Present

      Execute new product qualification Facilitate and manage qualification execution Develop qualification test program/sequence based on specifications and application usage model Perform Electrical Failure Analysis (EFA) and drive root cause and corrective action with other internal engineering groups Report data in a clear format including concise comments about findings Perform FA and risk assessment at all decision points within qualification cycle Collaborate to develop the DFMEA (Design Failure Mode Effect Analysis), DFT (Design For Testability), DFM (Design For Manufacturability) Continuously improve product quality and reliability through test development Develop and execute TFW for production, FA and NAND verification Develop clean code targeting embedded NAND and integrate with firmware developed by other team members Create unit tests and integrate with automation frameworks Aid in creation of test plans and assist in test activities related to characterization and benchmarking of SSD performance metrics Developing application level firmware and hardware libraries on a Cortex-M based processor using C and C++ Show less

    • Switzerland
    • Semiconductor Manufacturing
    • 300 - 400 Employee
    • Layout Design Engineer
      • Apr 2008 - Apr 2010

      Responsibilities and Tasks Develop New Memory and Memory Products Through the Design of the Overall Layout and Optimization of Memory Circuits - Study schematics to identify floor plan requirements and select optimized die size and block positioning - Create and coordinate layout schedules - Perform Assembly rule check as part of floor plan definition - Perform preliminary study of Design Rule Manual (DRM) to match technical requirements - Analyze block schematics to build up layout view - Perform design rule checks (DRCs) to ensure blocks conform to DRM - Perform Layout Versus Schematic (LVS) verification of measure blocks to conform to schematics Assist in the Development and Validation of Design Kit (DK) with Process Research and Development (Process R and D) and Computer Aided Drafting (CAD) Engineering - Support CAD group for DK validation - Collaborate with Process R and D engineering to define DK - Lead or participate in periodic Technical Requirement Definition Validation meetings with CAD and Process R and D Maintain Design Quality - Apply Design for Manufacturability (DFM) techniques to layouts - Provide robust layouts for critical signals, supply rails, and analog blocks - Design for layout efficiency Contribute to the Overall Success of the Layout Team - Mentor and provide consultation to internal and external team members - Organize, prioritize, and manage logistic and resource allocations - Troubleshoot technical design issues - Develop and maintain technical knowledge - Collaborate with CAD teams to select next generation software tools Show less

    • Switzerland
    • Semiconductor Manufacturing
    • 700 & Above Employee
    • Layout Design Engineer
      • Apr 2006 - Apr 2008

      Responsibilities and Tasks Develop New Memory and Memory Products Through the Design of the Overall Layout and Optimization of Memory Circuits - Study schematics to identify floor plan requirements and select optimized die size and block positioning - Create and coordinate layout schedules - Perform Assembly rule check as part of floor plan definition - Perform preliminary study of Design Rule Manual (DRM) to match technical requirements - Analyze block schematics to build up layout view - Perform design rule checks (DRCs) to ensure blocks conform to DRM - Perform Layout Versus Schematic (LVS) verification of measure blocks to conform to schematics Assist in the Development and Validation of Design Kit (DK) with Process Research and Development (Process R and D) and Computer Aided Drafting (CAD) Engineering - Support CAD group for DK validation - Collaborate with Process R and D engineering to define DK - Lead or participate in periodic Technical Requirement Definition Validation meetings with CAD and Process R and D Maintain Design Quality - Apply Design for Manufacturability (DFM) techniques to layouts - Provide robust layouts for critical signals, supply rails, and analog blocks - Design for layout efficiency Contribute to the Overall Success of the Layout Team - Mentor and provide consultation to internal and external team members - Organize, prioritize, and manage logistic and resource allocations - Troubleshoot technical design issues - Develop and maintain technical knowledge - Collaborate with CAD teams to select next generation software tools Show less

Education

  • Istituto Tecnico Industriale "Giambattista Bosco Lucarelli"
    Diploma Istituto Tecnico e Professionale, Tecnologia/tecnico di ingegneria elettrica, elettronica e delle comunicazioni
    1999 - 2004

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