Experience

Thalia

• United Kingdom
• Semiconductor Manufacturing
• 1 - 100 Employee

• Analog Layout Design Engineer

  • Sep 2021 - Present

  I was working as an Analog layout Engineer at Thalia and been working on various technologies like GF22nm, TSMC 40nm, 22nm, etc. I was working as an Analog layout Engineer at Thalia and been working on various technologies like GF22nm, TSMC 40nm, 22nm, etc.



Little Inventors Technologies Private Limited

• India
• E-Learning Providers
• 1 - 100 Employee

• STEM Instructor

  • Dec 2019 - Sep 2021

  I teach various courses like python, scratch, 3d-design, basic circuits etc at Little Inventors (www.littleinventors.in) , our mission is to encourage each child to imagine and unlock their full potential by experimenting and creativity in fun filled environment. I teach various courses like python, scratch, 3d-design, basic circuits etc at Little Inventors (www.littleinventors.in) , our mission is to encourage each child to imagine and unlock their full potential by experimenting and creativity in fun filled environment.



Blueberry Semiconductors Pvt. Ltd.

• India
• Semiconductor Manufacturing
• 1 - 100 Employee

• Analog layout engineer -Trainee

  • Sep 2018 - Sep 2019

  I worked as a Analog layout trainee for about 1 year, and have practiced layouts for blocks like op-amp, flip-flops oscillator, and blocks of PLL like PHFD & Divider, and designing standard cells from p-cells & also from scratch in various technologies like GPDK45nm & 90nm, TSMC45nm. And i have been exposed to physical verification tools like Diva & Calibre and running DRC, LVS, PERC, & PEX. And have learnt how to run post layout simulation. I worked as a Analog layout trainee for about 1 year, and have practiced layouts for blocks like op-amp, flip-flops oscillator, and blocks of PLL like PHFD & Divider, and designing standard cells from p-cells & also from scratch in various technologies like GPDK45nm & 90nm, TSMC45nm. And i have been exposed to physical verification tools like Diva & Calibre and running DRC, LVS, PERC, & PEX. And have learnt how to run post layout simulation.



MosChip Institute of Silicon Systems (M-ISS)

• India
• Professional Training and Coaching
• 1 - 100 Employee

• Analog Layout Engineer trainee

  • May 2018 - Aug 2018

  I have been trained as an Analog layout trainee engineer for a period of 4 months, and learnt the Fundamental concepts in MOSFET fundamentals, Second order effects, Fabrication concepts, Latch Up, Analog layout concepts like floor plan techniques, Device Matching techniques, Routing techniques (Power, Signal), Shielding concepts, Deep sub-micron process challenges like Well proximity, LOD and STI effects, ESD concepts and Layout guidelines. Physical verification concepts like LVS, DRC and Antenna with Parasitic extraction. Exposure to the Importance of reliability checks like EMIR analysis, DFM checks and ESD path checks. We get to work on 5 to 6 different designs in technolgies like GPDK45nm & TSMC180nm. I have learnt about developing layouts from schematics following the design constraints, process challenges and layout guidelines and verified the designs by the toos like ASSURA & PVS. Show less